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8530I-01 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8530I-01
Beschreibung 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 18 Seiten
8530I-01 Datasheet, Funktion
Low Skew, 1-to-16 Differential-to-3.3V
LVPECL Fanout Buffer
8530I-01
Datasheet
General Description
The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
8530I-01 ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
Sixteen differential 3.3V LVPECL output pairs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
Output skew: 75ps (maximum)
Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK0 Pulldown
nCLK0 Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
©2015 Integrated Device Technology, Inc.
Pin Assignment
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
VCCO
8530I-01
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
1 Revision B, December 1, 2015






8530I-01 Datasheet, Funktion
Parameter Measurement Information
2V
VCC,
VCCO
SCOPE
Qx
nQx
VEE
-1.3V ± -0.165V
LVPECL Output Load AC Test Circuit
8530I-01 Datasheet
VCC
nCLK
CLK
V
PP
VEE
Cross Points
Differential Input Level
V
CMR
nQx
Qx
nQy
Qy
Output Skew
Part 1
nQx
Qx
nQy Par t 2
Qy
t sk(pp)
Part-to-Part Skew
nCLK
CLK
nQ[0:15]
Q[0:15]
tPD
Propagation Delay
nQ[0:15]
Q[0:15]
Output Rise/Fall Time
©2015 Integrated Device Technology, Inc.
6
Revision B, December 1, 2015

6 Page









8530I-01 pdf, datenblatt
8530I-01 Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 8530I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8530I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 16 * 30mW = 480mW
Total Power_MAX (3.3V, with all outputs switching) = 519.75mW + 480mW = 999.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 34.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.0W * 34.1°C/W = 119.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 48 Lead TQFP, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.1°C/W
1
28.3°C/W
2.5
26.8°C/W
©2015 Integrated Device Technology, Inc.
12
Revision B, December 1, 2015

12 Page





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