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831752 Schematic ( PDF Datasheet ) - IDT

Teilenummer 831752
Beschreibung Clock Switch
Hersteller IDT
Logo IDT Logo 




Gesamt 18 Seiten
831752 Datasheet, Funktion
Clock Switch for ATCA/AMC and PCIe
Applications
831752
Data Sheet
General Description
The 831752 is a high-performance, differential HCSL clock switch.
The device is designed for the routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has one differential, bi-directional I/O (FCLK) for
connection to ATCA clock sources and to clock receivers through a
connector. The differential clock input CLK is the local clock input
and the HCSL output Q is the local clock output. In the common
clock mode, FCLK serves as an input and is routed to the differential
HCSL output Q. There are two local clock modes. In the local clock
mode 0, CLK is the input, Q is the clock output and FCLK is in
high-impedance state. In the local clock mode 1, CLK is the input
and both Q and FCLK are the outputs of the locally generated PCIe
clock signal. The 831752 is characterized to operate from a 3.3V
power or 2.5V power supply. The 831752 supports the switching of
PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
signals.
Pin Assignment
Features
Clock switch for PCIe and ATCA/AMC applications
Supports local and common ATCA/AMC clock modes
Bi-directional clock I/O FCLK:
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
Local HCSL clock output (Q)
Maximum input/output clock frequency: 500MHz
Maximum input/output data rate: 1000Mb/s (NRZ)
LVCMOS interface levels for the control inputs
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) 16-lead TSSOP package
-40°C to 85°C ambient operating temperature
DIR_SEL
nOEFCLK
VDD
FCLK
nFCLK
GND
CLK
nCLK
1
2
3
4
5
6
7
8
16 IREF
15 GND
14 VDD
13 Q
12 nQ
11 GND
10 VDD
9 nc
831752
16-lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package, Top View
Block Diagram
FCLK
nFCLK
50 50
22.33
22.33
CLK Pulldown
nCLK Pullup/Pulldown
nOEFCLK Pullup
DIR_SEL Pulldown
IREF
1=disable
1Q
nQ
0 50 50
©2016 Integrated Device Technology, Inc
1
Revision B June 28, 2016






831752 Datasheet, Funktion
Parameter Measurement Information
831752 Data Sheet
VDD
HCSL
IREF
GND
475Ω
0V
50Ω
50Ω
HCSL Output Load AC Test Circuit
SCOPE
1MΩ
1MΩ
VDD
nCLK,
nFCLK
CLK,
FCLK
V
PP
GND
Cross Points
V
CMR
Differential Input Levels
Spectrum of Output Signal Q
A0 MUX selects active
input clock signal
MUX_ISOL = A0 – A1
A1 MUX selects static input
Differential Measurement Points for Rise/Fall Edge Rate MUX_ISOLATION
ƒ
(fundamental)
Frequency
Single-ended Measurement Points for Absolute Cross
Point/Swing
Single-ended Measurement Points for Delta Cross Point
©2016 Integrated Device Technology, Inc
6
Revision B June 28, 2016

6 Page









831752 pdf, datenblatt
831752 Data Sheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Hts= H3s  H1sH2s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Ys= Xs  H3s  H1sH2s
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function
Ht.
PCIe Gen 2A Magnitude of Transfer Function
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
PCIe Gen 1 Magnitude of Transfer Function
©2016 Integrated Device Technology, Inc
12
Revision B June 28, 2016

12 Page





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