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831742I Schematic ( PDF Datasheet ) - IDT

Teilenummer 831742I
Beschreibung 4:2 Differential Clock/Data Multiplexer
Hersteller IDT
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Gesamt 20 Seiten
831742I Datasheet, Funktion
4:2 Differential Clock/Data
Multiplexer
831742I
Data Sheet
General Description
The 831742I is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has four differential, selectable clock/data inputs. The
selected input signal is distributed to two low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831742I is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831742I ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831742I supports the clock multiplexing and
distribution of PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and
Gen 3 (8 Gb/s) clock signals.
Features
4:2 differential clock/data multiplexer with fanout
Four selectable, differential input pairs
Each differential input pair can accept the following levels: HCSL,
LVDS and LVPECL
Two differential HCSL output pairs
Maximum input/output clock frequency: 700MHz
Maximum input/output data rate: 1400Mb/s (NRZ)
LVCMOS interface levels for all control inputs
PCI Express (2.5Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
jitter compliant
Input skew: 110ps max
Part-to-part skew: 225ps max
Full 3.3V supply voltage
Available in lead-free (RoHS 6)
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
Pulldown
CLK0 Pullup/down
nCLK0 Pulldown
Pullup/down
Pulldown
CLK1 Pullup/down
nCLK1
Pulldown
Pullup/down
CLK2 Pulldown
nCLK2 Pulldown
CLK3
Pullup
Pullup
nCLK3
00
01
10
11
QA
nQA
Pin Assignment
GND
CLK0
nCLK0
VDD
CLK1
nCLK1
CLK2
nCLK2
GND
CLK3
nCLK3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
24 SEL1
23 IREF
22 SEL0
21 VDD
20 nQB
19 QB
18 nQA
17 QA
16 VDD
15 GND
14 nOEB
13 nOEA
831742AGI
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
April 5, 2016






831742I Datasheet, Funktion
831742I Data Sheet
Table 5B. HCSL AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
fOUT
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 16
Across All Outputs
tsk(i)
Input Skew; NOTE 13
Any Input to Q/nQ
tsk(pp)
Part-to-Part Skew; NOTE 14, 15
MUXISOL
Rising
Edge Rate
Mux Isolation
Rising Edge Rate; NOTE 2, 3
f = 100MHz
f = 100MHz
Falling
Edge Rate
Falling Edge Rate; NOTE 2, 3
f = 100MHz
VRB
VMAX
Ringback Voltage; NOTE 2, 4
Absolute Max Output Voltage;
NOTE 5, 6
f = 100MHz
f = 100MHz
VMIN
Absolute Min Output Voltage;
NOTE 5, 7
f = 100MHz
VCROSS
Absolute Crossing Voltage;
NOTE 5, 8, 9
f = 100MHz
VCROSS
Total Variation of VCROSS over all
edges; NOTE 5, 8, 10
f = 100MHz
odc Output Duty Cycle; NOTE 11
f 200MHz
Minimum
1.5
Typical
2
3
30
40
Maximum
700
2.5
15
110
225
Units
MHz
ns
ps
ps
ps
dB
0.6 4 V/ns
0.6
-100
4
100
1150
V/ns
mV
mV
-300
mV
250 550 mV
140 mV
48 50 52 %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input cross point to the differential output crossing point.
NOTE 2: Measurement taken from differential waveform.
NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from QX minus nQX). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 4: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB = ±100 differential range. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of QX equals the falling edge of nQX.
See Parameter Measurement Information Section
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of rising QX and falling nQX. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 11: Input duty cycle must be 50%.
NOTE 12: Matching applies to rising edge rate for QX and falling edge rate for nQX. It is measured using a ±75mV window centered on the
median crosspoint where QX meets nQX falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope is to use
for the edge rate calculations. The rise edge rate of QX should be compared to the fall edge rate of nQX, the maximum allowed difference
should not exceed 20% of the slowest edge rate.
NOTE 13: Defined as skew between input paths on the same device, using the same input signal levels, measured at one specific output at the
differential cross points.
NOTE 14: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 15: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 16: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
©2016 Integrated Device Technology, Inc
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April 5, 2016

6 Page









831742I pdf, datenblatt
831742I Data Sheet
Recommended Termination
Figure 3A is the recommended source termination for applications
where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output
types.
All traces should be 50impedance single-ended or 100
differential.
0.5" Max
L1
Rs
22 to 33 +/-5%
0-0.2"
L2
PCI Expres s
Driver
L1
L2
0-0.2" L3 L3
1-14"
L4
L4
PCI Expres s
Connector
0.5 - 3.5"
L5
L5
PCI Expres s
Add-in Card
Rt 49.9 +/- 5%
Figure 3A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
Figure 3B is the recommended termination for applications where a
point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a
matched termination at the receiver, transmission-line reflections will
be minimized. In addition, a series resistor (Rs) at the driver offers
flexibility and can help dampen unwanted reflections. The optional
resistor can range from 0to 33. All traces should be 50
impedance single-ended or 100differential.
0.5" Max
L1
L1
PCI Expres s
Driver
Rs
0 to 33
0 to 33
0-18"
L2
L2
Rt
0-0.2"
L3
L3
49.9 +/- 5%
Figure 3B. Recommended Termination (where a point-to-point connection can be used)
©2016 Integrated Device Technology, Inc
12
April 5, 2016

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