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Teilenummer | 8312 |
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Beschreibung | 1-to-12 LVCMOS/LVTTL Fanout Buffer | |
Hersteller | IDT | |
Logo | ||
Gesamt 18 Seiten Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
8312
Datasheet
General Description
The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312 single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312 ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
• Twelve LVCMOS/LVTTL outputs
• CLK input supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
• 0°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
CLK Pulldown
D
Q
LE
OE Pullup
12
Q[0:11]
©2015 Integrated Device Technology, Inc
1
Pin Assignment
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
8312
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
December 11, 2015
8312 Datasheet
Table 4G. LVCMOS/LVTTL DC Characteristics, TA = 0°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH Input High Voltage
VIL Input Low Voltage
CLK
IIH
Input
High Current
OE, CLK_EN
VDD = 3.465V
VDD = 2.625V
VDD = 2.0V
VDD = 3.465V
VDD = 2.625V
VDD = 2.0V
VDD = VIN = 3.465V or
2.625V or 2.0V
VDD = VIN = 3.465V or
2.625V or 2.0V
2
1.7
0.65*VDD
-0.3
-0.3
-0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
1.3
0.7
0.35*VDD
150
5
V
V
V
V
V
V
µA
µA
IIL
Input
Low Current
CLK
OE, CLK_EN
VDD = 3.465V or 2.625V or 2.0V,
VIN = 0V
VDD = 3.465V or 2.625V or 2.0V,
VIN = 0V
-5
-150
VDDO = 3.3V ± 5%
2.6
VDDO = 2.5V ± 5%;
1.8
VOH Output High Voltage; NOTE 1
VDDO = 2.5V ± 5%; IOH = -1mA
2
VDDO = 1.8V ± 0.2V
VDD – 0.3
VDDO = 1.8V ± 0.2V; IOH = -100µA VDD – 0.2
VDDO = 3.3V ± 5%
VDDO = 2.5V ± 5%;
VOL Output Low Voltage; NOTE 1
VDDO = 2.5V ± 5%; IOL = 1mA
VDDO = 1.8V ± 0.2V
VDDO = 1.8V ± 0.2V; IOL = 100µA
µA
µA
V
V
V
V
V
0.5 V
0.45 V
0.4 V
0.35 V
0.2 V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.
©2015 Integrated Device Technology, Inc
6
December 11, 2015
6 Page Parameter Measurement Information, continued
V
DDO
Qx 2
V
DDO
Qy 2
t sk(o)
Output Skew
Part 1
Qx
V
DDO
2
Part 2
Qy
V
DDO
2
t sk(pp)
Part-to-Part Skew
8312 Datasheet
CLK
Q0:Q11
VDD
2
VDDO
2
tpLH
Propagation Delay
VDD
2
VDDO
2
tpHL
Q0:Q11
VDDO
2
t PW
odc = t PW
t PERIOD
VDDO
2
t PERIOD
Output Duty Cycle/Pulse Width/Period
VDDO
2
20%
Q0:Q11
80%
tR
Output Rise/Fall Time
80%
tF
20%
©2015 Integrated Device Technology, Inc
12
December 11, 2015
12 Page | ||
Seiten | Gesamt 18 Seiten | |
PDF Download | [ 8312 Schematic.PDF ] |
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831-91-016-64-001 | PCB connectors 2.0 mm Single row / double row Press-fit | Precid-Dip Durtal SA |
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