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830154I-08 Schematic ( PDF Datasheet ) - IDT

Teilenummer 830154I-08
Beschreibung Over-Voltage Tolerant 1.5V 1:4 Fanout Buffer
Hersteller IDT
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Gesamt 17 Seiten
830154I-08 Datasheet, Funktion
Over-Voltage Tolerant 1.5V, 1:4
Fanout Buffer
830154I-08
Data Sheet
General Description
The 830154I-08 is an LVCMOS, over-voltage tolerant clock fanout
buffer targeted for clock generation in high-performance
telecommunication, networking and computing applications. The
device is optimized for low-skew clock distribution in low-voltage
applications. The input over-voltage tolerance enables using this
device in mixed-mode voltage applications. An output enable pin
controls whether the outputs are in the active or high impedance
state. Guaranteed output skew characteristics make the 830154I-08
ideal for those applications demanding well defined performance and
repeatability. The 830154I-08 is packaged in a small 8-TSSOP and
in an 8-SOIC package.
Features
Low-skew 1:4 fanout buffer
Supports 3.3V, 2.5V, 1.8V and 1.5V power supplies
LVCMOS input and output levels
3.6V Over-voltage tolerance at the clock and control inputs
Supports clock frequencies up to 160MHz
LVCMOS compatible control input for output disable
Output disabled to a high-impedance state
-40°C to 85°C ambient operating temperature
Available in lead-free RoHS 6 packages (8-TSSOP, 8-SOIC)
Block Diagram
CLK_IN
Pulldown
Pullup
OE
Q1
Pin Assignments
Q2
CLK_IN 1
8 OE
Q1 2
7 VDD
Q3
Q2 3
6 GND
Q3 4
5 Q4
Q4 830154AMI-08
8-SOIC, 150 mil
3.9mm x 4.9mm x 1.375mm package body
M-Package
Top View
830154AGI-08
8-TSSOP
4.4mm x 3.0mm x 0.925mm package body
G-Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 30, 2016






830154I-08 Datasheet, Funktion
830154I-08 Data Sheet
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tpLH
Output Frequency
Propagation Delay
(low to high transition); NOTE 1
tpHL
Propagation Delay
(high to low transition); NOTE 1
tPLZ, tPHZ
Disable Time
(active to high-impedance)
tPZL, tPZH
Enable Time
(high-impedance to disable)
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
10% to 90%
Minimum
0.8
Typical
Maximum
160
1.7
Units
MHz
ns
0.8 1.7 ns
10 ns
10
250
800
0.076
0.35 1.2
48 52
ns
ps
ps
ps
ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to FOUT 150MHz.
NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
Table 5C. AC Characteristics, VDD = 1.8V ± 0.15V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tpLH
Output Frequency
Propagation Delay
(low to high transition); NOTE 1
tpHL
Propagation Delay
(high to low transition); NOTE 1
tPLZ, tPHZ
Disable Time
(active to high-impedance)
tPZL, tPZH
Enable Time
(high-impedance to disable)
tsk(o)
Output Skew; NOTE 2, 3
tsk(pp)
tjit
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.63V to 1.17V
For NOTES, see Table 5B above.
Minimum
1.1
Typical
Maximum
160
2.1
Units
MHz
ns
1.1 2.1 ns
10 ns
10
250
800
0.193
0.12 0.6
47 53
ns
ps
ps
ps
ns
%
©2016 Integrated Device Technology, Inc
6
Revision A March 30, 2016

6 Page









830154I-08 pdf, datenblatt
830154I-08 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 830154I-08.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the830154I-08 is the sum of the core power plus the power dissipation in the load(s). The following is the power
dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V *1mA = 3.465mW
Total Static Power:
= Power (core)MAX = 3.465mW
Dynamic Power Dissipation at FOUT_MAX (160MHz)
Total Power (160MHz) = [(CPD * N) * Frequency * (VDDO)2] = [(14pF *4) * 160MHz * (3.465V)2] = 107.6mW
N = number of outputs
Total Power
= Static Power + Dynamic Power Dissipation
= 3.465mW + 107.6mW
= 111.065mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 121.5°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.111W *121.5°C/W = 98.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
121.5°C/W
1
117.3°C/W
2.5
115.3°C/W
Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection
JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
1
94°C/W
2.5
89°C/W
©2016 Integrated Device Technology, Inc
12
Revision A March 30, 2016

12 Page





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