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PDF DS2432 Data sheet ( Hoja de datos )
| Número de pieza | DS2432 | |
| Descripción | 1Kb Protected 1-Wire EEPROM | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS2432 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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ABRIDGED DATA SHEET
DS2432
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
FEATURES
1128 Bits of 5V EEPROM Memory
Partitioned Into Four Pages of 256 Bits, a
64-Bit Write-Only Secret, and Up to Five
General-Purpose Read/Write Registers
On-Chip 512-Bit ISO/IEC 10118-3 SHA-1
Engine to Compute 160-Bit Message
Authentication Codes (MACs) and to
Generate Secrets
Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting a 160-Bit MAC as
Authorization
Secret and Data Memory Can Be Write
Protected (All or Page 0 Only) or Put in
EPROM-Emulation Mode (“Write to 0”,
Page 1)
Unique, Factory-Lasered and Tested 64-Bit
Registration Number Assures Absolute
Traceability Because No Two Parts Are Alike
Built-In Multidrop Controller Ensures
Compatibility with Other 1-Wire® Net
Products
Reduces Control, Address, Data, and Power
to a Single Data Pin
Directly Connects to a Single Port Pin of a
Microprocessor and Communicates at Up to
15.3kbps
Overdrive Mode Boosts Communication
Speed to 90.9kbps
Low-Cost 6-Lead TSOC Surface-Mount
Package or Solder-Bumped UCSP™ Package
Reads and Writes Over a Wide Voltage
Range of 2.8V to 5.25V from -40°C to +85°C
PIN CONFIGURATIONS
TOP VIEW
GND 1
1-Wire 2
NC 3
TSOC
(150 mils)
6 NC
5 NC
4 NC
A1 MARK
UCSP
(TOP VIEW WITH LASER
A DS2432
MARK, CONTACTS NOT
VISIBLE)
B
yywwrr
A2 = 1-WIRE
C ###xx
A3 = GND
ALL OTHER BUMPS: NC
1234
yywwrr = DATE/REVISION
###xx = LOT NUMBER
REFER TO THE PACKAGE RELIABILITY REPORT FOR
IMPORTANT GUIDELINES ON QUALIFIED USAGE CONDITIONS.
ORDERING INFORMATION
PART
TEMP
RANGE
PIN-
PACKAGE
DS2432P+
-40°C to +85°C 6 TSOC
DS2432P+T&R -40°C to +85°C 6 TSOC
DS2432X-S+
-40°C to +85°C
8 UCSP (2.5k
pcs, T&R)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Request Full Data Sheet at:
www.maximintegrated.com/DS2432
1-Wire is a registered trademark and UCSP is a trademark of Maxim Integrated Products, Inc.
1 of 17
219-0003; Rev 9/12
1 page  
ABRIDGED DATA SHEET
1-Wire CRC GENERATOR Figure 4
Polynomial = X8 + X5 + X4 + 1
DS2432
1st 2nd 3rd 4th
STAGE STAGE STAGE STAGE
X0 X1 X2 X3
5th
STAGE
X4
6th 7th 8th
STAGE STAGE STAGE
X5 X6
X7
INPUT DATA
X8
MEMORY MAP
The DS2432 has four memory areas: data memory, secrets memory, register page with special function
registers and user-bytes, and a scratchpad. The data memory is organized in pages of 32 bytes. Secret,
register page and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data
memory, loading the initial secret or when writing to the register page. For further details (including
Figure 5) refer to the full version of the data sheet.
ADDRESS REGISTERS AND TRANSFER STATUS
The DS2432 employs three address registers: TA1, TA2 and E/S (Figure 6). These registers are common
to many other 1-Wire devices but operate slightly differently with the DS2432. Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data will be read.
Register E/S is a read-only transfer-status register, used to verify data integrity with write commands.
Since the scratchpad of the DS2432 is designed to accept data in blocks of eight bytes only, the lower
three bits of TA1 will be forced to 0 and the lower three bits of the E/S register (Ending Offset) will
always read 1. This indicates that all the data in the scratchpad will be used for a subsequent copying into
main memory or secret. Bit 5 of the E/S register, called PF or “partial byte flag”, is a logic-1 if the
number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not
valid due to a loss of power. A valid write to the scratchpad will clear the PF bit. Bits 3, 4 and 6 have no
function; they always read 1. The Partial Flag supports the master checking the data integrity after a
Write command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as
a flag to indicate that the data stored in the scratchpad has already been copied to the target memory
address. Writing data to the scratchpad clears this flag.
ADDRESS REGISTERS Figure 6
Bit # 7 6 5 4 3 2
Target Address (TA1) T7
T6
T5
T4
T3
T2
(0)
Target Address (TA2) T15 T14 T13 T12 T11 T10
Ending Address with
Data Status (E/S) AA 1 PF 1
(Read Only)
1
E2
(1)
1
T1
(0)
T9
E1
(1)
0
T0
(0)
T8
E0
(1)
5 of 17
5 Page 
ABRIDGED DATA SHEET
DS2432
Overdrive Match ROM [69h]
The Overdrive Match ROM command, followed by a 64-bit registration number transmitted at Overdrive
Speed, allows the bus master to address a specific DS2432 on a multidrop bus and to simultaneously set it
in Overdrive Mode. Only the DS2432 that exactly matches the 64-bit number will respond to the
subsequent memory or SHA-1 function command. Slaves already in Overdrive mode from a previous
Overdrive Skip or a successful Overdrive Match command will remain in Overdrive mode. All Over-
drive-capable slaves will return to regular speed at the next Reset Pulse of minimum 480 µs duration. The
Overdrive Match ROM command can be used with a single or multiple devices on the bus.
Resume Command [A5h]
In a typical application the DS2432 needs to be accessed several times to write a full 32-byte page. In a
multidrop environment this means that the 64-bit registration number of a Match ROM command has to
be repeated for every access. To maximize the data throughput in a multidrop environment the Resume
Command function was implemented. This function checks the status of the RC bit and, if it is set,
directly transfers control to the Memory and SHA-1 functions, similar to a Skip ROM command. The
only way to set the RC bit is through successfully executing the Match ROM, Search ROM or Overdrive
Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume
Command function. Accessing another device on the bus will clear the RC bit, preventing two or more
devices from simultaneously responding to the Resume Command function.
1-Wire SIGNALING
The DS2432 requires strict protocols to ensure data integrity. The protocol consists of four types of sig-
naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data.
Except for the presence pulse the bus master initiates all these signals. The DS2432 can communicate at
two different speeds, regular speed and Overdrive Speed. If not explicitly set into the Overdrive mode,
the DS2432 will communicate at regular speed. While in Overdrive Mode the fast timing applies to all
waveforms.
The initialization sequence required to begin any communication with the DS2432 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2432 is ready to send or receive data. The
bus master transmits (TX) a reset pulse (tRSTL, minimum 480 µs at regular speed, 48 µs at Overdrive
Speed). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled
to a high state via the pullup resistor. After detecting the rising edge on the data pin, the DS2432 waits
(tPDH, 15-60 µs at regular speed, 2-6 µs at Overdrive speed) and then transmits the Presence Pulse (tPDL,
60-240 µs at regular speed, 8-24 µs at Overdrive Speed). A Reset Pulse of 480 µs or longer will exit the
Overdrive Mode returning the device to regular speed. If the DS2432 is in Overdrive Mode and the Reset
Pulse is no longer than 80 µs the device will remain in Overdrive Mode.
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS2432.PDF ] | |
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