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8413S12I-100 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8413S12I-100
Beschreibung Clock Generator
Hersteller IDT
Logo IDT Logo 




Gesamt 30 Seiten
8413S12I-100 Datasheet, Funktion
Clock Generator for Cavium
Processors
8413S12I-100
Data Sheet
General Description
Features
The 8413S12I-100 is a PLL-based clock generator specifically
designed for Cavium Networks Octeon II processors. This high
performance device is optimized to generate the processor core
reference clock, the PCI-Express reference clocks and the clocks for
both the Gigabit Ethernet MAC and PHY. The clock generator offers
ultra low-jitter, low-skew clock outputs, and edge rates that easily
meet the input requirements for the CN63XX and CN68XX series of
processors. The output frequencies are generated from a 25MHz
external input source or an external 25MHz parallel resonant crystal.
The industrial temperature range of the 8413S12I-100 supports
telecommunication, networking, and storage requirements.
Applications
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Ten 100MHz clocks for PCI Express, HCSL interface levels
One single-ended QG LVCMOS/LVTTL clock output at 125MHz
One single-ended QF LVCMOS/LVTTL clock output at 50MHz,
15output impedance
Two single-ended QREFx LVCMOS/LVTTL outputs at 25MHz,
15output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Supply Modes, (125MHz QG output and 25MHz QREFx outputs):
Core / Output
3.3V / 3.3V
3.3V / 2.5V
Supply Modes, (HCSL outputs, and 50MHz QF output):
Core / Output
3.3V / 3.3V
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Pin Assignment
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
VDDA
nc
nc
XTAL_IN
XTAL_OUT
nc
REF_SEL
GND
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
1 54
2 53
3 52
4 51
5 50
6 8XXXXXX
7
49
48
8 47
9
10
8413S12I-100
46
45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
nc
VDD
IREF
OE_D
nQD1
QD1
nQD0
QD0
VDDO_D
VDDO_C
nQC1
QC1
nQC0
QC0
OE_C
VDD
GND
nc
©2016 Integrated Device Technology, Inc.
72-pin, 10mm x 10mm LQFP Package
1 October 4, 2016






8413S12I-100 Datasheet, Funktion
8413S12I-100 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
XTAL_IN
Other Inputs
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
4.6V
0V to VDD
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
25.4°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_[A:E] = VDDO_[F:G] = VDDO_QREF = 3.3V ± 5%,
TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load, CLK selected
3.135
VDD 0.16
3.135
3.3
3.3
3.3
86
13
76
3.465
VDD
3.465
103
16
91
NOTE: VDDO_X denotes VDDO_[A:E], VDDO_[F:G}, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_[A:E], IDDO_[F:G], IDDO_QREF
Units
V
V
V
mA
mA
mA
Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO_G = VDDO_QREF = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
VDDA
VDDO_X
IDD
IDDA
IDDO_X
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load, CLK selected
3.135
VDD 0.16
2.375
3.3
3.3
2.5
79
13
50
3.465
VDD
2.625
95
16
60
V
V
V
mA
mA
mA
NOTE: VDDO_X denotes VDDO_G, VDDO_QREF.
NOTE: IDDO_X denotes IDDO_G, IDDO_QREF.
©2016 Integrated Device Technology, Inc.
6
October 4, 2016

6 Page









8413S12I-100 pdf, datenblatt
Parameter Measurement Information
8413S12I-100 Data Sheet
1.65V±5%
1.65V±5%
VDD,
VDDO_[F:G],
VDDO_QREF VDDA
GND
SCOPE
Qx
2.05V±5%
1.25V±5%
2.05V±5%
VDD
VDDO_G,
2
VDDO_QREF
VDDA
GND
SCOPE
Qx
-1.65V±5%
-1.25V±5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
3.3V±5%
3.3V±5%
VDD,
VDDO_[A:E]
VDDA
3.3V±5%
3.3V±5%
VDD,
VDDO_[A:E]
VDDA
VDDA
3.3V Core/3.3V HCSL Output Load AC Test Circuit
This load condition is used for IDD and tjit(Ø) measurements.
3.3V Core/3.3V HCSL Output Load AC Test Circuit
VDD
nCLK
CLK
V
PP
GND
Cross Points
Differential Input Level
V
CMR
RMS Phase Jitter
©2016 Integrated Device Technology, Inc.
12
October 4, 2016

12 Page





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