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PDF BU9795BGUW Data sheet ( Hoja de datos )
| Número de pieza | BU9795BGUW | |
| Descripción | Low Duty LCD Segment Driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Low Duty LCD Segment Driver
BU9795BGUW MAX 124 segments (SEG31×COM4)
General Description
BU9795BGUW is a 1/4 duty general-purpose LCD driver
that can be used for consumer / battery operated
products and can drive up to 124 LCD Segments.
It has integrated display RAM for reducing CPU load.
Also, it is designed with low power consumption and no
external component needed.
Its small BGA package is well-suited for small footprint
applications.
Features
Integrated RAM for display data (DDRAM) :
31 × 4bit (Max 124 Segment)
LCD drive output :
4 Common output, Max 31Segment output
Integrated Buffer AMP for LCD driving
Integrated Oscillator circuit
No external components
Low power consumption Design
Applications
Metering
Home automation goods
White goods
Small appliances
Healthcare products
Battery operated products
etc.
Key Specifications
■ Supply Voltage Range:
+2.5V to +5.5V
■ Operating Temperature Range: -40°C to +85°C
■ Max Segments:
124 Segments
■ Display Duty:
1/4
■ Bias:
1/2, 1/3 selectable
■ Interface:
3wire serial interface
Package
W (Typ) x D (Typ) x H (Max)
VBGA049W040A
4.00mm x 4.00mm x 0.80mm
Typical Application Circuit
VDD
C > 0.1uF
Controller
Insert Capacitors
between VDD and VSS
VDD
VLCD
INHb
CSB
SD
SCL
OSCIN
TEST
VSS
COM0
COM1
COM2
COM3
SEG2
SEG3
SEG32
Internal Oscillator Circuit Mode
Figure 1. Typical Application Circuit
Segment
LCD
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111･14･001
○This product has no designed protection against radioactive rays.
1/25
TSZ02201-0P4P0D301490-1-2
25.Apr.2016 Rev.001
1 page  
BU9795BGUW MAX 124 segments (SEG31×COM4)
Electrical Characteristics – continued
MPU Interface Characteristics (VDD=2.5V to 5.5V, VSS=0V, Ta=-40°C to +85°C, unless otherwise specified)
Parameter
Symbol
Min
Limit
Typ
Unit
Max
Conditions
Input Rise Time
tr -
- 80 ns
Input Fall Time
tf -
- 80 ns
SCL Cycle Time
“H” SCL Pulse Width
“L” SCL Pulse Width
tSCYC
tSHW
tSLW
400
100
100
-
-
-
- ns
- ns
- ns
SD Setup Time
tSDS 20
-
- ns
SD Hold Time
tSDH 50
-
- ns
CSB Setup Time
tCSS 50
-
- ns
CSB Hold Time
tCSH 50
-
- ns
“H” CSB Pulse Width
tCHW 50
-
- ns
tCHW
CSB
SCL
tCSS
tf
tSLW
tSCYC
tSHW
tSDS tSDH
tr
tCSH
SD
I/O Equivalent Circuit
VDD
VLCD
VSS
CSB, SD, SCL
VSS
VDD
INHb
VSS
VDD
SEG/COM
VSS
Figure 5. Interface Timing
TEST
VSS
OSCIN
VSS
VDD
VSS
Figure 6. I/O Equivalent Circuit
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
5/25
TSZ02201-0P4P0D301490-1-2
25.Apr.2016 Rev.001
5 Page 
BU9795BGUW MAX 124 segments (SEG31×COM4)
(1)
CSB
COMMAND
Internal Signal
ICSET P2
Internal Signal
Address
ADSET”00010” RAM Write RAM Write RAM Write
・・・・・
RAM Write
DISCTL RAM Write RAM Write ・・・ RAM Write
000010 000011 000100 ・・・ 100010 000000 000001 000010
000011 000100 000101
Set address by ADSET command.
P2(ICSET command) is refer to set address.
Address will be set "000010", because P2(ICSET)="0".
When RAM data is continuously transmitted,
address will be increment automatically.
When write at 22h address, address will be
return to 00h automatically.
Because of no setting ADSET command,
it will maintain the previous address.
It will start to write RAM data from maintained address.
The following address that write at the end is maintained.
(2)
CSB
COMMAND
Internal Signal
ICSET P2
Internal Signal
Address
ADSET ”11111” RAM Write RAM Write RAM Write
・・・・・
RAM Write
ADSET”00000”RAM Write RAM Write ・・・ RAM Write
011111 100000 100001 100010 000000 000001 000010 000011
000000 000001 000010 000011
Set address by ADSET command.
P2(ICSET command) is refer to set address.
Address will be set "011111", because P2(ICSET)="0".
New address will be set by ADSET command.
When RAM data is continuously transmitted,The following address that write at the end is maintained.
address will be increment automatically.
When write at 22h address, address will
return to 00h automatically.
(3)
CSB
COMMAND
Internal Signal
ICSET P2
Internal Signal
Address
ICSET P2=1 ADSET ”00000” RAM Write RAM Write
・・・・・
RAM Write
ADSET”00000” RAM Write RAM Write ・・・ RAM Write
100000 100001 100010 000000 000001 000010 000011
100000 100001 100010 000000
Set address by ADSET command.
P2(ICSET command) is refer to set address.
New address will be set by ADSET command.
Address will be set "100000", because P2(ICSET)="1".
Address will be set "100000", because P2(ICSET)="1".
(P2(ICSET) will maintain the previous address
until ICSET command input.
It will be set P2="1" by ICSET command.
When RAM data is continuously transmitted,
(ICSET command cannot set address)
address will be increment automatically. The following address that write at the end is maintained.
When write at 22h address, address will be
return to 00h automatically.
(4)
CSB
COMMAND
Internal Signal
ICSET P2
Internal Signal
Address
ICSET P2=1 ADSET ”00000” RAM Write RAM Write
・・・・・
RAM Write
ICSET P2=0 RAM Write RAM Write ・・・ RAM Write
100000 100001 100010 000000
・・・・・
100000 100001
100010 000000 000001
Set address by ADSET command.
P2(ICSET command) is refer to set address.
It is written to RAM continuously
from the previous address.
The address maintain the previous address
When RAM data is continuously transmitted,
because it doesn't input the ADSET command
address will be increment automatically.
though ICSET P2="0" setting.
When write at 22h address, address will be
return to 00h automatically.
The following address that write at the end is maintained.
Figure 13. Address Set Sequence
www.rohm.com
© 2016 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
11/25
TSZ02201-0P4P0D301490-1-2
25.Apr.2016 Rev.001
11 Page | ||
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