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N24C32 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer N24C32
Beschreibung 32 Kb I2C CMOS Serial EEPROM
Hersteller ON Semiconductor
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Gesamt 10 Seiten
N24C32 Datasheet, Funktion
N24C32
32 Kb I2C CMOS Serial
EEPROM
Description
The N24C32 is a 32 Kb CMOS Serial EEPROM device, organized
internally as 128 pages of 32 bytes each. This device supports the
Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C
protocol.
Data is written by providing a starting address, then loading 1 to 32
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
N24C32 devices on the same bus.
Features
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V / 1.6 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Fast Write Time (4 ms max)
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Automotive Grade 1 Temperature Range
US 8−lead Package
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
www.onsemi.com
US8
U SUFFIX
CASE 493
PIN CONFIGURATIONS
A0
A1
A2
VSS
1
VCC
WP
SCL
SDA
US8 (U)
(Top View)
MARKING DIAGRAM
8
XX MG
G
1
XX = Specific Device Code*
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
* See Ordering Information section for the
Specific Device Marking Code
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 1
1
Publication Order Number:
N24C32/D






N24C32 Datasheet, Funktion
SCL FROM
MASTER
N24C32
BUS RELEASE DELAY (TRANSMITTER)
18
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (tAA)
Figure 4. Acknowledge Timing
ACK SETUP (tSU:DAT)
tF tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SDA IN
SDA OUT
tAA tDH
Figure 5. Bus Timing
tSU:STO
tBUF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri-stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow-up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The N24C32 is shipped erased, i.e., all bytes are FFh.
www.onsemi.com
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