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PDF MC44724 Data sheet ( Hoja de datos )

Número de pieza MC44724
Descripción Digital Video Encoder
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MC44724 Hoja de datos, Descripción, Manual

Advance Information
Digital Video Encoder
RGB Output Support
HCMOS Technology
The MC44724 and MC44725 are Digital Video Encoders (DVE).
They convert ITU-601/656 standard 4:2:2 Bit-Paralellel data into
analog composite video, S-Video or Y/Cb/Cr or R/G/B in PAL
and NTSC formats. They accept the multiplexed ((CB,Y,CR)Y)
signals from digital sources such as MPEG decoders and can act as
a sync generator master. All video processing is done digitally and
requires no external adjustment.
Specifically designed for digital satellite, digital cable decoders
and multimedia terminals.
MC44724
MC44725
• World Wide Operation (PAL-BDGHI, PAL-N,PAL-M, NTSC-M)
VFU SUFFIX
• SMPTE 170M / ITU - R 624 composite video output
• Programmable Color Sub-carrier Frequencies
64 VQFP
(0.5mm Pitch)
• Analog Horizontal, Vertical, Frame or Composite Sync Outputs
• Sync Extraction From Digital Input Data (SAV, EAV)
• Sync Polarity and Horizontal Phase Control
• Master or Slave Sync (H/Vsync, H/Fsync, ITU-R656 Slave) Operation
• Interlaced or Non-Interlaced Support
• 625/50 or 525/60 ITU-601/656 two 8-bit or 16-bit ((CB,Y,CR)Y) Digital Input
• Luma 2X / Chroma 4X Oversampling Filtering
External VBI Information Data Input (such as TeleText Information Data)
• Selectable Two sets of Signals within (CVBS/Y/C) or (Y/Cb/Cr) or (R/G/B)
Six Analog Outputs Through 10-bit DACs
• Easily programmed via Serial Bus ( I2C or SPI Bus)
2 Hardware I2C Chip Addresses
Closed-Caption, CGMS and WSS Information data Insertion
MACROVISION ver. 7.01 Anti-Copy Signal Insertion(MC44724 Only)
• On Chip Color - bar Generator
+3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply
The MC44724 device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098
and other intellectual property rights. The use of Macrovision's copy protection technology in the
device must be authorized by Macrovision and is intended for home and other limited pay-per-
view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or
disassembly is prohibited.
No. 1
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.

1 page




MC44724 pdf
[Function Descriptions]
Clock
27.0Mhz is necessary. This signal on the clock pin needs to be active before the reset pin is de-asserted.
( see figures 1 and 2 )
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE
clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/
NTSC, TVIN and SEL pins.
The PAL/NTSC pin determines the default values for the DVE control registers. The default register
values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately
when a valid input digital video data stream is present.
The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus
operation. If High, the DVE use 4-wired SPI operation.
After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled.
(see page --- for sub-address register descriptions.)
Fig 1 : DVIN Data Input Timing
Input Clock 27MHz
Input Data
DVIN0~7
50%
Tds
Tdh
Fig 2 : Sync Data Output Timing
Clock 27MHz
Output Data
TP0~8
Output data
H/VF sync
Td
Td
No. 5
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.

5 Page





MC44724 arduino
Chroma / Luma Encoding
The DVE de-multiplexes the 4:2:2 digital video data stream.
The de-multiplexed Y or Luma samples are interpolated (2X oversampled) at the clock rate. Offset
compensation is then added, next any VBI signals consisting of Closed-Caption, CGMS and WSS are
added to the appropriate lines, then finally composite sync pulses are added to the Luma signal.
(see figure 12.)
De-multiplexed component color CB and CR samples are interpolated (4X oversampled) at the clock rate.
Interpolating simplifies the output filter and allows more accurate encoding. The DVE generates the
necessary subcarrier color frequency for PAL or NTSC encoding from the 27Mhz system clock. This
color subcarrier is then modulated by the base band component color CB and CR signals to create the
video Chroma signal. (see figure 13.)
A 7.5 IRE pedestal is added for the 60Hz field rate. This can be added for the 50Hz field rate through
serial bus control. (see sub-address register descriptions)
CVBS and S-VIDEO or YCbCr or RGB Outputs
The internal digital video signals drive 10-bit D/A converters. Converter outputs are bi-directional current
sources where the current is proportional to the digital data with reference to the IBIAS reference current. The
pins CVBS/Cb/B, Y/G and C/Cr/R are the respective composite, Luma and Chroma or Y/Cb/Cr or R/G/B signal
current source pins. Also, each DACs can drive 75ohm load register.
User can select 2 sets of signals within above 3 sets.
(see "Application Diagram" and "sub-address register descriptions".)
Bias Current Gain
DACs can be switched off through serial bus control to reduce power consumption. Both outputs of unused
DACs should be connected to ground through a resister to avoid charge buildup.
No. 11
MC44724/5 Rev 0.21 03/25/97
This document contains information on a new product. Specifications and information herein are subject to change without notice.

11 Page







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