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AD7152 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7152
Beschreibung 12-Bit Capacitance-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD7152 Datasheet, Funktion
Data Sheet
12-Bit Capacitance-to-Digital Converter
AD7152/AD7153
FEATURES
Capacitance-to-digital converters
Interfaces to floating sensors
Resolution down to 0.25 fF (that is, up to 12 ENOB)
Linearity: 0.05%
Common-mode (not changing) capacitance up to 5 pF
Four capacitance ranges selectable per operation mode
±0.25 pF to ±2 pF in differential mode
0.5 pF to 4 pF in single-ended mode
Tolerant of parasitic capacitance to ground up to 50 pF
Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms
Internal clock oscillator
2-wire serial interface (I2C-compatible)
Power
2.7 V to 3.6 V single-supply operation
100 μA current consumption
Operating temperature: −40°C to +85°C
10-lead MSOP
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Level sensing
Flowmeters
Humidity sensing
FUNCTIONAL BLOCK DIAGRAMS
VDD
CIN1(+)
CIN1(–)
EXC1
CIN2(+)
CIN2(–)
EXC2
CAP+
CAP–
AD7152
CLOCK
VOLTAGE
GENERATOR REFERENCE
MUX
12-BIT Σ-
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 1.
VDD
CAP+
CAP–
AD7153
CLOCK
VOLTAGE
GENERATOR REFERENCE
CIN1(+)
CIN1(–)
EXC1
MUX
12-BIT Σ-
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 2.
GENERAL DESCRIPTION
The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-to-
digital converters (CDCs). The capacitance to be measured is
connected directly to the device inputs. The architecture features
inherent high resolution (12-bit no missing codes, up to 12-bit
effective resolution) and high linearity (±0.05%). The AD7152/
AD7153 have four capacitance input ranges per operation mode,
±0.25 pF to ±2 pF in differential mode and 0.5 pF to 4 pF in
single-ended mode.
The AD7152/AD7153 can accept up to 5 pF common-mode
capacitance (not changing), which can be balanced by a
programmable on-chip, digital-to-capacitance converter
(CAPDAC).
The AD7153 has one capacitance input channel, while the
AD7152 has two channels. Each channel can be configured
as single-ended or differential. The AD7152/AD7153 are
designed for floating capacitive sensors.
The AD7152/AD7153 have a 2-wire, I2C-compatible serial
interface. Both devices can operate with a single power supply
from 2.7 V to 3.6 V. They are specified over the temperature
range of −40°C to +85°C and are available in a 10-lead MSOP.
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD7152 Datasheet, Funktion
AD7152/AD7153
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Positive Supply Voltage, VDD to GND
Voltage on Any Input or Output Pin to GND
ESD Rating (ESD Association Human
Body Model, S5.1)
ESD Rating (Field-Induced Charged
Device Model)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
MSOP
θJA Thermal Impedance-to-Air
θJC Thermal Impedance-to-Case
Reflow Soldering (Pb-Free)
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +3.9 V
−0.3 V to VDD + 0.3 V
4 kV
750 V
−40°C to +85°C
−65°C to +150°C
150°C
206°C/W
44°C/W
260 (+0/−5)°C
10 sec to 40 sec
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 6 of 24

6 Page









AD7152 pdf, datenblatt
AD7152/AD7153
The user can also access any unique register (address) on a
one-to-one basis without having to update all the registers.
However, the address pointer register contents cannot be read.
If an incorrect address pointer location is accessed, or if the user
allows the autoincrementer to exceed the required register
address, apply the following requirements:
In read mode, the AD7152/AD7153 continue to output
various internal register contents until the master device
issues a no acknowledge, start, or stop condition. The
contents of the address pointers autoincrementer are reset
to point to the status register at Address 0x00 when a stop
condition is received at the end of a read operation. This
allows the status register to be read (polled) continually
without having to constantly write to the address pointer.
In write mode, the data for the invalid address is not
loaded into the registers of the AD7152/AD7153, but
an acknowledge is issued by the AD7152/AD7153.
Data Sheet
AD7152/AD7153 RESET
To reset the AD7152/AD7153 without having to reset the entire
I2C bus, an explicit reset command is provided. This command
uses a particular address pointer word as a command word to
reset the device and upload all default settings. The AD7152/
AD7153 do not respond to the I2C bus commands (no acknowl-
edge) during the default values upload for approximately 150 μs
(maximum 200 μs).
The reset command address word is 0xBF.
GENERAL CALL
When a master issues a slave address consisting of seven 0s with
the eighth bit (R/W bit) set to 0, this is called the general call
address. The general call address is for addressing every device
connected to the I2C bus. The AD7152/AD7153 acknowledge
this address and read the following data byte.
If the second byte is 0x06, the AD7152/AD7153 are reset,
completely uploading all default values. The AD7152/AD7153
do not respond to the I2C bus commands (no acknowledge)
during the default values upload for approximately 150 μs
(maximum 200 μs).
The AD7152/AD7153 do not acknowledge any other general call
commands.
SDA
SCL S
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
START ADDR R/W ACK SUBADDRESS
ACK
DATA
ACK
Figure 22. Bus Data Transfer
P
STOP
WRITE
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR
LSB = 0
A(S)
DATA
A(S)
LSB = 1
READ
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
DATA
A(M)
A(S) P
DATA
A(M) P
Table 5. I2C Abbreviation
Abbreviation
S
P
A(S)
A(M)
A(S)
A(M)
ACK
R/W
Figure 23. Write and Read Sequences
Definition
Start bit
Stop bit
Acknowledge by slave
Acknowledge by master
No acknowledge by slave
No acknowledge by master
Acknowledge
Read/write
Rev. A | Page 12 of 24

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