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9DBV0841 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9DBV0841
Beschreibung 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Hersteller IDT
Logo IDT Logo 




Gesamt 16 Seiten
9DBV0841 Datasheet, Funktion
8-output 1.8V PCIe Gen1-3
Zero-Delay/Fan-out Buffer w/Zo=100ohms
9DBV0841
DATASHEET
Description
The 9DBV0841 is a 1.8V member of IDT's full featured PCIe
family. It has integrated output terminations providing
Zo=100for direct connection for 100transmission lines.
The device has 8 output enables for clock management and 3
selectable SMBus addresses.
Recommended Application
SSD, microServers, WLAN Access points
Output Features
8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 32 resistors; minimal board space
and BOM cost
62mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SS
Compatible
PLL
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0841 APRIL 28, 2016
1 ©2016 Integrated Device Technology, Inc.






9DBV0841 Datasheet, Funktion
9DBV0841 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Output Supply Voltage
Ambient Operating
Temperature
VDDIO
TAMB
Supply voltage for Low Power HCSL Outputs
Commmercial range
Industrial range
Input High Voltage
VIH
Single-ended inputs, except SMBus
Input Mid Voltage
VIM
Single-ended tri-level inputs ('_tri' suffix)
Input Low Voltage
VIL
Single-ended inputs, except SMBus
Input Current
IIN Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IINP VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Fibyp
Bypass mode
Input Frequency
Fipll
Fipll
100MHz PLL mode
125MHz PLL mode
Fipll 50MHz PLL mode
Pin Inductance
Lpin
Capacitance
CIN
CINDIF_IN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
COUT
Output pin capacitance
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of single-ended control inputs
Trise
tR Rise time of single-ended control inputs
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
Bus Voltage
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
6The differential input clock must be running for the SMBus to be active
1.7
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
-200
1
60
75
30
1.5
1.5
30
0
1
2.1
4
1.7
1.8
1.05
25
25
1.9
1.9
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
200 uA
200 MHz
100.00 140
MHz
125.00 175
MHz
50.00 65 MHz
7 nH
5 pF
2.7 pF
6 pF
0.6 1 ms
33 kHz
66 kHz
3 clocks
300
5
0.6
3.6
0.4
3.6
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
2
2
2
2
1
1
1,5
1
1,2
1,3
1,3
2
2
4
1
1
6
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
6 APRIL 28, 2016

6 Page









9DBV0841 pdf, datenblatt
9DBV0841 DATASHEET
Marking Diagrams
ICS
DBV0841AL
YYWW
COO
LOT
ICS
BV0841AIL
YYWW
COO
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
PARAMETER
Thermal Resistance
1ePad soldered to board
SYMBOL
CONDITIONS
θJC
θJb
θJA0θ
θJA1
θJA3
θJA5
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NDG48
TYP
VALUE
33
2.1
37
30
27
26
UNITS NOTES
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
8-OUTPUT 1.8V PCIE GEN1-3 ZERO-DELAY/FAN-OUT BUFFER W/ZO=100OHMS
12 APRIL 28, 2016

12 Page





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