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9DBV0741 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9DBV0741
Beschreibung 7-output 1.8V HCSL Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 17 Seiten
9DBV0741 Datasheet, Funktion
7-output 1.8V HCSL Fanout Buffer
w/Zo=100ohms
9DBV0741
DATASHEET
Description
The 9DBV0741 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100ohm
transmission lines.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
7 – 1-200MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
100ohm direct connect; saves 28 resistors and 48mm2
compared to standard HCSL
41mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0741 REVISION B 03/28/16 1 ©2016 Integrated Device Technology, Inc.






9DBV0741 Datasheet, Funktion
9DBV0741 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Output Supply Voltage
VDDIO
Low Voltage Supply LP-HCSL Outputs
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
TCOM
TIND
VIH
VIM
VIL
IIN
IINP
Fin
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
6DIF_IN input
7The differential input clock must be running for the SMBus to be active
1.7
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
1.8
1.05-1.8
25
25
1.9
1.9
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
-200
200 uA
1 200 MHz
7 nH
1.5 5 pF
1.5 2.7 pF
6 pF
1 ms
30 33 kHz
0 66 kHz
1 3 clocks
300 us
5 ns
5 ns
0.8 V
2.1 3.3 V
0.4 V
4 mA
1.7 3.6 V
1000
ns
300 ns
400 kHz
1
1
2
1
1
1,6
1
1,2
1,3
1,3
2
2
4
5
1
1
7
7-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS
6
REVISION B 03/28/16

6 Page









9DBV0741 pdf, datenblatt
9DBV0741 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Bit 7
RID3
Bit 6
Bit 5
RID2
RID1
Revision ID
Bit 4
RID0
Bit 3
VID3
Bit 2
Bit 1
VID2
VID1
VENDOR ID
Bit 0
VID0
Type
R
R
R
R
R
R
R
R
01
A rev = 0000
0001 = IDT
Default
0
0
0
0
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Name
Bit 7
Device Type1
Bit 6
Device Type0
Bit 5
Device ID5
Bit 4
Device ID4
Bit 3
Device ID3
Bit 2
Device ID2
Bit 1
Device ID1
Bit 0
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FG, 01 = DB
10 = DM, 11= DB fanout only
000111 binary or 07 hex
Default
1
1
0
0
0
1
1
1
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
BC4
Bit 3
BC3
Bit 2
BC2
Bit 1
BC1
Bit 0
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
7-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS
12
REVISION B 03/28/16

12 Page





SeitenGesamt 17 Seiten
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