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9DBU0731 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9DBU0731
Beschreibung 7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 17 Seiten
9DBU0731 Datasheet, Funktion
7 O/P 1.5V PCIe Gen1-2-3 Fan-out Buffer
9DBU0731
DATASHEET
Description
The 9DBU0731 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
7 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is <300fs rms for PCIe Gen3
DIF additive phase jitter <350s rms for SGMII
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
LP-HCSL outputs; save 14 resistors compared to standard
HCSL outputs
36mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins for each output; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device operation
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
` DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0731 REVISION C 04/22/15
1
©2015 Integrated Device Technology, Inc.






9DBU0731 Datasheet, Funktion
9DBU0731 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Output Supply Voltage
VDDIO
Low Voltage Supply LP-HCSL Outputs
Ambient Operating
Temperature
TAMB
Commmercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
IIN
IINP
Fin
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
1.425
0.95
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
1.5
1.05-1.5
25
25
1.575
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
-200
200 uA
1 167 MHz
7 nH
1.5 5 pF
1.5 2.7 pF
6 pF
1 ms
30
0
1
2.1
4
1.425
33 kHz
66 kHz
3 clocks
300
5
5
0.6
3.3
0.4
3.3
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
2
1
1
1,5
1
1,2
1,3
1,3
2
2
4
1
1
6
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
6
REVISION C 04/22/15

6 Page









9DBU0731 pdf, datenblatt
9DBU0731 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Bit 7
RID3
Bit 6
Bit 5
RID2
RID1
Revision ID
Bit 4
RID0
Bit 3
VID3
Bit 2
Bit 1
VID2
VID1
VENDOR ID
Bit 0
VID0
Type
R
R
R
R
R
R
R
R
01
A rev = 0000
0001 = IDT
Default
0
0
0
0
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Name
Bit 7
Device Type1
Bit 6
Device Type0
Bit 5
Device ID5
Bit 4
Device ID4
Bit 3
Device ID3
Bit 2
Device ID2
Bit 1
Device ID1
Bit 0
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FGx, 01 = DBx,
10 = DMx, 11= DBx w/oPLL
000111 binary or 07 hex
Default
1
1
0
0
0
1
1
1
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
BC4
Bit 3
BC3
Bit 2
BC2
Bit 1
BC1
Bit 0
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
12
REVISION C 04/22/15

12 Page





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