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9DBU0241 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9DBU0241
Beschreibung 2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
Hersteller IDT
Logo IDT Logo 




Gesamt 17 Seiten
9DBU0241 Datasheet, Funktion
2 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBU0241
DATASHEET
Description
The 9DBU0241 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 2 output enables for clock
management.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
2 – 1-167MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
Direct connection to 100transmission lines; saves 8
resistors compared to standard HCSL outputs
35mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
vOE(1:0)#
2
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF1
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
9DBU0241 REVISION C 04/22/15 1 ©2015 Integrated Device Technology, Inc.






9DBU0241 Datasheet, Funktion
9DBU0241 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
VDDx
Supply voltage for core and analog
Ambient Operating
Temperature
TAMB
Commmercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
fMODINPCIe
fMODIN
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
Tdrive_PD#
tLATOE#
tDRVPD
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
6The differential input clock must be running for the SMBus to be active
1.425
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
-200
1
20
1.5
1.5
30
0
1
2.1
4
1.425
TYP
1.5
25
25
MAX UNITS NOTES
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
°C
°C
V
V
V
uA
1
1
200 uA
100.00
167
110
7
5
2.7
6
1
MHz
MHz
nH
pF
pF
pF
ms
2
2
1
1
1,5
1
1,2
33 kHz
66 kHz
3 clocks 1,3
300 us 1,3
5
5
0.6
3.3
0.4
3.3
1000
300
ns
ns
V
V
V
mA
V
ns
ns
2
2
4
1
1
400 kHz 6
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
6
REVISION C 04/22/15

6 Page









9DBU0241 pdf, datenblatt
9DBU0241 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
01
A rev = 0000
0001 = IDT
Default
0
0
0
0
0
0
0
1
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
Control Function
Device Type
Device ID
Type
R
R
R
R
R
R
R
R
01
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
000100 binary or 02 hex
Default
0
1
0
0
0
0
1
0
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC4
BC3
BC2
BC1
BC0
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
0
1
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW = 8 bytes.
RW
Default
0
0
0
0
1
0
0
0
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
12
REVISION C 04/22/15

12 Page





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