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Teilenummer | 9DB1933 |
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Beschreibung | Nineteen Output Differential Buffer | |
Hersteller | IDT | |
Logo | ||
Gesamt 17 Seiten Nineteen Output Differential Buffer for PCIe Gen3
DATASHEET
9DB1933
Recommended Application
19 output PCIe Gen3 zero-delay/fanout buffer
General Description
The 9DB1933 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1933 is driven by a differential SRC output
pair from an IDT 932S421, 932SQ420, or equivalent, main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
• 19 - 0.7V current mode differential HCSL output pairs
Features/Benefits
• 8 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 11 dedicated and 3 group OE# pins/Hardware control of the
outputs
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode
for power management
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 150 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Functional Block Diagram
OE(17_18)#
OE(15_16)#
OE(14:5)#,
OE_01234#
13
DIF_IN
DIF_IN#
HIGH_BW#
CKPWRGD/PD#
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
Logic
PLL
(SS Compatible)
19
DIF(18:0)
IREF
IDT® Nineteen Output Differential Buffer for PCIe Gen3
1
1676A—07/12/10
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
Electrical Characteristics - Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage - DIF_IN VIHDIF
Differential inputs
(single-ended measurement)
Input Low Voltage - DIF_IN VILDIF
Differential inputs
(single-ended measurement)
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value
Measured differentially
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle
dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
MIN TYP
600 800
VSS - 300
0
300
300
0.4
-5
45
0
MAX
1150
UNITS NOTES
mV 1
300 mV 1
1000
1450
8
5
55
125
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
1
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
Trf
∆Trf
Scope averaging on
Slew rate matching, Scope averaging on
1 2 4 V/ns 1, 2, 3
20 % 1, 2, 4
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 789 850
using oscilloscope math function. (Scope averaging
mV
on) -150 45 150
1
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using absolute
value. (Scope averaging off)
-300
834
17
1150
mV
1
1
Vswing
Vswing
Scope averaging off
300 744
mV 1, 2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 380 550 mV 1, 5
Crossing Voltage (var)
∆-Vcross
Scope averaging off
24 140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH =
6 x IREF and VOH = 0.7V @ ZO=50Ω (100Ω differential impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses
for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Operating Supply Current IDD3.3OP
All outputs active @100MHz, CL = Full load;
Powerdown Current
IDD3.3PDZ
All differential pairs tri-stated
1Guaranteed by design and characterization, not 100% tested in production.
427 500 mA 1
32 40 mA 1
IDT® Nineteen Output Differential Buffer for PCIe Gen3
6
1676A—07/12/10
6 Page 9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
General SMBus serial interface information for the 9DB1933
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address DD(h)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
Note: Addresses show assumes pin 29 is low.
IDT® Nineteen Output Differential Buffer for PCIe Gen3
N Not acknowledge
P stoP bit
Byte N + X - 1
1676A—07/12/10
12
12 Page | ||
Seiten | Gesamt 17 Seiten | |
PDF Download | [ 9DB1933 Schematic.PDF ] |
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