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PDF 49LF008A Data sheet ( Hoja de datos )

Número de pieza 49LF008A
Descripción SST49LF008A
Fabricantes Silicon Storage Technology 
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A Microchip Technology Company
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
The SST49LF008A flash memory devices are designed to be read-compatible
with the Intel® 82802 Firmware Hub (FWH) device for PC-BIOS application.
These devices provide protection for the storage and update of code and data in
addition to adding system design flexibility through five general purpose inputs.
Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH)
Interface mode for in-system programming and Parallel Programming (PP) mode
for fast factory programming of PC-BIOS applications.
Features
• Firmware Hub for Intel 8xx Chipsets
• 8 Mbit SuperFlash memory array for code/data
storage
– 1024K x8
• Flexible Erase Capability
– Uniform 4 KByte Sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top Boot Block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance:100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Firmware Hub Interface (FWH) Mode for
In-System operation
– Parallel Programming (PP) Mode for fast
production programming
• Firmware Hub Hardware Interface Mode
– 5-signal communication interface supporting byte Read
and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protect for entire chip and/or top Boot Block
– Block Locking Register for all blocks
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Writedetection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and
8-pin data I/O interface
– Supports fast In-System or PROM programming for
manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 40-lead TSOP (10mm x 20mm)
– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25085A
10/11

1 page




49LF008A pdf
A Microchip Technology Company
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
NC (NC)
IC (IC)
NC (NC)
NC (NC)
NC (NC)
NC (NC)
A10 (FGPI4)
NC (NC)
R/C# (CLK)
VDD
NC (NC)
RST# (RST#)
NC (NC)
NC (NC)
A9 (FGPI3)
A8 (FGPI2)
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Standard Pinout
Top View
Die Up
( ) Designates FWH Mode
Figure 4: Pin Assignments for 40-lead TSOP
40 VSS
39 VDD
38 (FWH4) WE#
37 (INIT#) OE#
36 (NC) NC
35 (RES) DQ7
34 (RES) DQ6
33 (RES) DQ5
32 (RES) DQ4
31 (NC) NC
30 VSS
29 VSS
28 (FWH3) DQ3
27 (FWH2) DQ2
26 (FWH1) DQ1
25 (FWH0) DQ0
24 (ID0) A0
23 (ID1) A1
22 (ID2) A2
21 (ID3) A3
1232 40-tsop P1.0
©2011 Silicon Storage Technology, Inc.
5
DS25085A
10/11

5 Page





49LF008A arduino
A Microchip Technology Company
8 Mbit Firmware Hub
SST49LF008A
Data Sheet
Table 4: FWH Write Cycle
Clock Field Field Contents
Cycle Name
FWH[3:0]1
FWH[3:0]
Direction
Comments
1 START
1110
IN FWH4 must be active (low) for the part to respond. Only
the last start field (before FWH4 transitions high) should
be recognized. The START field contents indicate a FWH
memory Read cycle.
2 IDSEL 0000 to 1111
IN Indicates which SST49LF008A device should respond.
If the IDSEL (ID select) field matches the value
ID[3:0], then that particular device will respond to the
whole bus cycle.
3-9 IMADDR
YYYY
IN These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
10 IMSIZE 0000 (1 byte)
IN This size field indicates how many bytes will be trans-
ferred during multi-byte operations. The FWH only
supports single-byte writes. IMSIZE=0000b
11 DATA
YYYY
IN This field is the least-significant nibble of the data byte.
This data is either the data to be programmed into the
flash memory or any valid flash command.
12 DATA
YYYY
IN This field is the most-significant nibble of the data byte.
13 TAR0
1111
IN then Float
In this clock cycle, the master (Intel ICH) has driven the
then float bus to all ‘1’s and then floats the bus prior to
the next clock cycle. This is the first part of the bus “turn-
around cycle.”
14 TAR1 1111 (float) Float then OUT The SST49LF008A takes control of the bus during this
cycle. During the next clock cycle it will be driving the
“sync” data.
15 RSYNC
0000
OUT
The SST49LF008A outputs the values 0000, indicating
that it has received data or a flash command.
16 TAR0
1111
OUT then Float
In this clock cycle, the SST49LF008A has driven the bus
to all then float ‘1’s and then floats the bus prior to the
next clock cycle. This is the first part of the bus “turn-
around cycle.”
17 TAR1
1111 (float)
Float then IN The master (Intel ICH) resumes control of the bus during this
cycle.
1. Field contents are valid on the rising edge of the present clock cycle.
T4.4 25085
CLK
FWH4
FWH[3:0]
STR IDS
Figure 7: Write Waveforms
IMADDR
IMS DATA
TAR RSYNC
TAR
1161 F10.0
©2011 Silicon Storage Technology, Inc.
11
DS25085A
10/11

11 Page







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