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Teilenummer | 9FGU0641 |
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Beschreibung | 6 O/P 1.5V PCIe Gen1-2-3 Clock Generator | |
Hersteller | IDT | |
Logo | ||
Gesamt 15 Seiten 6 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0641
DATASHEET
Description
The 9FGU0641 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100ohms. The device has 6 output enables for
clock management and supports 2 different spread spectrum
levels in addition to spread off.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
• 6 -100MHz Low-power HCSL (LP-HCSL) DIF pairs
w/Zo=100
• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <60ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is < 3.0ps RMS
Block Diagram
Features/Benefits
• Direct connection to 100ohm transmission lines; saves 24
resistors compared to standard PCIe device
• 45mW typical power consumption; reduced thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 40-pin 5x5 mm VFQFPN; minimal board
space
X1_25
X2
vOE(5:0)#
OSC
REF1.8
6
DIF5
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0641 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.
9FGU0641 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
Output Supply Voltage
VDDIO Supply voltage for differential Low Power Outputs
Ambient Operating
Temperature
TAMB
Comercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
VIH
VIL
IIN
IINP
Fin
Lpin
CIN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended outputs, except SMBus. IOH = -2mA
Single-ended outputs, except SMBus. IOL = -2mA
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
Logic Inputs, except DIF_IN
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency
OE# Latency
fMOD
tLATOE#
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
1.425 1.5 1.575
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
VDD-0.45
-5
1.05-1.5
25
25
0.5 VDD
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
0.45
5
V
V
°C
°C
V
V
V
V
V
uA
-200 200 uA
23 25 27 MHz
7 nH
1.5 5 pF
6 pF
1.8 ms
30 31.6 33 kHz
1 3 clocks
2.1
4
1.425
300
5
5
0.6
3.3
0.4
3.3
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1,2
1
1,3
1,3
2
2
4
1
1
1
6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
6
OCTOBER 18, 2016
6 Page 9FGU0641 DATASHEET
Thermal Characteristics
PARAMETER SYMBOL
Thermal Resistance
1ePad soldered to board
θJC
θJb
θJA0
θJA1
θJA3
θJA5
CONDITIONS
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NDG40
TYP.
42
2.4
39
33
28
27
Marking Diagrams
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
1
1
1
1
1
1
ICS
GU0641AL
YYWW
COO
LOT
ICS
U0641AIL
YYWW
COO
LOT
Notes:
1. “LOT” is the lot number.
2. “COO” denotes the country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number.
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature grade.
6 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
12
OCTOBER 18, 2016
12 Page | ||
Seiten | Gesamt 15 Seiten | |
PDF Download | [ 9FGU0641 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
9FGU0641 | 6 O/P 1.5V PCIe Gen1-2-3 Clock Generator | IDT |
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