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9FGU0241 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9FGU0241
Beschreibung 2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
Hersteller IDT
Logo IDT Logo 




Gesamt 15 Seiten
9FGU0241 Datasheet, Funktion
2 O/P 1.5V PCIe Gen1-2-3 Clock Generator
w/Zo=100ohms
9FGU0241
DATASHEET
Description
The 9FGU0241 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family with integrated output terminations
providing Zo=100. The device has 2 output enables for
clock management, 2 different spread spectrum levels in
addition to spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 clock generator
Output Features
2 - 100MHz Low-Power (LP) HCSL DIF pairs w/Zo=100
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard PCIe devices
23mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 24-pin 4x4 mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vOE(1:0)#
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF1
DIF0
9FGU0241 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.






9FGU0241 Datasheet, Funktion
9FGU0241 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
Ambient Operating
Temperature
TAMB
Comercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
VIH
VIL
IIN
IINP
Fin
Lpin
CIN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended outputs, except SMBus. IOH = -2mA
Single-ended outputs, except SMBus. IOL = -2mA
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
Logic Inputs, except DIF_IN
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency
OE# Latency
fMOD
tLATOE#
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
1.425
0
-40
0.75 VDD
0.4 VDD
-0.3
VDD-0.45
-5
-200
23
1.5
30
1
2.1
4
1.425
1.5 1.575
25
25
0.5 VDD
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
0.45
5
V
°C
°C
V
V
V
V
V
uA
200 uA
25 27 MHz
7 nH
5 pF
6 pF
1.8 ms
31.6
33 kHz
3 clocks
300
5
5
0.6
3.3
0.4
3.3
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1,2
1
1,3
1,3
2
2
4
1
1
1
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
6
OCTOBER 18, 2016

6 Page









9FGU0241 pdf, datenblatt
9FGU0241 DATASHEET
Thermal Characteristics
PARAMETER
Thermal Resistance
1ePad soldered to board
SYMBOL
CONDITIONS
θJC Junction to Case
θJb Junction to Base
θJA0 Junction to Air, still air
θJA1 Junction to Air, 1 m/s air flow
θJA3 Junction to Air, 3 m/s air flow
θJA5 Junction to Air, 5 m/s air flow
PKG
NLG24
TYP
VALUE
UNITS
NOTES
62 °C/W
1
5.4 °C/W
1
50 °C/W
1
43 °C/W
1
39 °C/W
1
38 °C/W
1
Marking Diagrams
LOT
U41AL
YYWW
LOT
U41AIL
YYWW
Notes:
1. “LOT” is the lot number.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. “L” denotes RoHS compliant package.
4. “I” denotes industrial temperature grade.
2 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS
12
OCTOBER 18, 2016

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