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9FGV0441 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9FGV0441
Beschreibung 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Hersteller IDT
Logo IDT Logo 




Gesamt 15 Seiten
9FGV0441 Datasheet, Funktion
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
DATASHEET
9FGV0441
Description
The 9FGV0441 is an 4-output very low power clock
generator for PCIe Gen1-2-3 applications with integrated
output terminations providing Zo=100. The device has 4
output enables for clock management and supports 2
different spread spectrum levels in addition to spread off.
Recommended Application
PCIe Gen1-2-3 Clock Generator
Output Features
4 - 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs w/Zo=100
1 - 1.8V LVCMOS REF output w/ Wake-On-Lan (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
Integrated terminations provide 100differential Zo;
reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
X1_25
X2
OE(3:0)#
OSC
REF1.8
SS Capable PLL
4
DIF(3:0)
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
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9FGV0441 Datasheet, Funktion
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
1.8V Supply Voltage
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
VDDx1.8
Supply voltage for core, analog and single-ended
LVCMOS outputs
1.7
TIND Industrial range -40
VIH
Single-ended inputs, except SMBus
0.75 VDD
VIM Single-ended tri-level inputs ('_tri' suffix, if present) 0.4 VDD
1.8 1.9 V
25 85 °C
VDD + 0.3
0.6 VDD
V
V
1
1
1
1
Input Low Voltage
Schmitt Trigger Postive
Going Threshold Voltage
VIL
VT+
Single-ended inputs, except SMBus
Single-ended inputs, where indicated
Schmitt Trigger Negative
Going Threshold Voltage
VT-
Single-ended inputs, where indicated
Hysteresis Voltage
VH
VT+ - VT-
Output High Voltage
VIH Single-ended outputs, except SMBus. IOH = -2mA
Output Low Voltage
VIL Single-ended outputs, except SMBus. IOL = -2mA
Input Current
IIN Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IINP VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Fin
XTAL, or X1 input
Pin Inductance
Lpin
Capacitance
CIN
COUT
Logic Inputs, except DIF_IN
Output pin capacitance
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency
fMOD
Allowable Frequency
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of single-ended control inputs
Trise
tR Rise time of single-ended control inputs
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
-0.3
0.4 VDD
0.1 VDD
0.1 VDD
VDD-0.45
-5
-200
23
1.5
31
2
2.1
4
1.7
25
0.6
31.6
3
4
0.25 VDD
0.7 VDD
0.4 VDD
0.4 VDD
0.45
5
V
V
V
V
V
V
uA
200 uA
27 MHz
7 nH
5 pF
6 pF
1.8 ms
32 kHz
4 clocks
300
5
5
0.8
3.6
0.4
3.6
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1
1
1
1
1
1
1
1
1
1,2
1
1,3
1,3
1,2
1,2
1,4
1,5
1
1
1
1
1
1
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
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9FGV0441
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9FGV0441 pdf, datenblatt
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
Thermal Characteristics
PARAMETER SYMBOL
Thermal Resistance
1ePad soldered to board
θJC
θJb
θJA0
θJA1
θJA3
θJA5
CONDITIONS
Junction to Case
Junction to Base
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
PKG
NLG32
TYP.
42
2.4
39
33
28
27
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
1
1
1
1
1
1
Marking Diagrams
ICS
V0441AIL
YYWW
COO
LOT
ICS
GV0441AL
YYWW
COO
LOT
Notes:
1. Line 2 is the truncated part number.
2. ‘L’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
5. ‘COO’ denotes country of origin.
6. ‘LOT’ is the lot number.
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
12
9FGV0441
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12 Page





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