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9FGP204 Schematic ( PDF Datasheet ) - IDT

Teilenummer 9FGP204
Beschreibung FREQUENCY TIMING GENERATOR
Hersteller IDT
Logo IDT Logo 




Gesamt 18 Seiten
9FGP204 Datasheet, Funktion
DATASHEET
Frequency Timing Generator for Peripherals
9FGP204
Recommended Application:
Peripheral Clock for Intel Server
Output Features:
• 1 - 0.7V current-mode differential CPU pair
• 6 - 50MHz RMII outputs
• 2 - 125MHz RGMII outputs
• 1 - DOT 96MHz output
• 1 - 33.33MHz output
• 1 - 32.768KHz output
• 2 - 25MHz REF outputs
Key Specifications:
• Exact synthesis on CPU, RGMII, RMII & 33.33MHz
clocks
• +/- 100ppm frequency accuracy on other clocks
Features/Benefits:
• Selectable SMBus Address - D0/D1 or C0/C1
• Spread Spectrum capability on CPU and DOT 96MHz
clocks
• SMBus Control:
- M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
- Differential outputs can be disabled via pins or SMBus
Pin Configuration
40 39 38 37 36 35 34 33 32 31
GND 1
30 GNDRMII
VDD96 2
29 RMII2
DOT96SST 3
28 RMII3
DOT96SSC 4
27 GNDRMII
OE_96 5
OE_CPU 6
9FGP204
26 VDDRMII
25 RMII4
CPUCLKT0 7
24 RMII5
CPUCLKC0 8
23 VDD33
VDDCPU 9
22 33.33MHZ/**SMBADR
GNDCPU 10
21 GND33
11 12 13 14 15 16 17 18 19 20
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Dow n Resistor
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0 MHz
MHz
0 0 0 266.67 96.00
0 0 1 133.33 96.00
0 1 0 200.00 96.00
0 1 1 166.67 96.00
1 0 0 333.33 96.00
1 0 1 100.00 96.00
1 1 0 400.00 96.00
1 1 1 Reserved 96.00
Power up default is highlighted.
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
RGMII
MHz
125.00
125.00
125.00
125.00
125.00
125.00
125.00
125.00
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
SMBus Address Selection
SMBADR
*SMBADR = 0 SMBADR = 1
D0/D1
C0/C1
* Default value
IDT® Frequency Timing Generator for Peripherals
1
1604B—08/29/11






9FGP204 Datasheet, Funktion
9FGP204
Frequency Timing Generator for Peripherals
Table2: DOT96 Spread and Frequency Selection Table
DOT96
SS_EN
FS3
FS2
FS1
FS0
Byte 0
Byte 3
Byte 3
Byte 3
Byte 3
bit 4 bit 3 bit 2 bit 1 bit 0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
DOT96SS
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
Spread %
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
+/-0.25 Center
+/-0.5 Center
+/-0.75 Center
+/-1.0 Center
-0.25 Down
-0.50 Down
-0.75 Down
-1.0 Down
-1.25 Down
-1.50 Down
-1.75 Down
-2.0 Down
-2.25 Down
-2.5 Down
-2.75 Down
-3.00 Down
IDT® Frequency Timing Generator for Peripherals
6
1604B—08/29/11

6 Page









9FGP204 pdf, datenblatt
9FGP204
Frequency Timing Generator for Peripherals
General SMBus serial interface information for the 9FGP204
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D0 (H)
• ICS clock will acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address *D0(H)
WR WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
ACK
ACK
ACK
ACK
Byte N + X - 1
P stoP bit
ACK
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address *D0(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address *D1(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
* The SMBus address depends on the latched value of pin 22.
Please see SMBus Address Selection table on page 1.
N Not acknowledge
P stoP bit
Byte N + X - 1
IDT® Frequency Timing Generator for Peripherals
12
1604B—08/29/11

12 Page





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