9FGP202A Datasheet PDF - IDT
| Part Number | 9FGP202A | |
| Description | FREQUENCY TIMING GENERATOR | |
| Manufacturers | IDT | |
| Logo |  |
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There is a preview and 9FGP202A download ( pdf file ) link at the bottom of this page. Total 19 Pages | ||
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FREQUENCY TIMING GENERATOR FOR PERIPHERALS
DATASHEET
9FGP202A
General Description
The 9FGP202A is a peripheral clock for Intel Server. It is
driven with a 25MHz crystal and generates CPU outputs up
to 400MHz. An SMBus interface allows full control of the
device.
Recommended Application
Peripheral Clock for Intel Server
Output Features
• 1 - 0.7V current-mode differential CPU pair
• 8 - 50MHz output
• 1 - DOT 96MHz output
• 1 - 33.33MHz output
• 1 - 32.768KHz output
• 2 - 25MHz REF outputs
Block Diagram
Features/Benefits
• Selectable SMBus Address – D0/D1 or C0/C1
• Spread Spectrum capability on CPU and DOT 96MHz
clocks
• SMBus Control:
– M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
– Outputs can be disabled via pins or SMBus
Key Specifications
• Exact synthesis on CPU, RMII and 33.33MHz clocks
• +/- 100ppm frequency accuracy on remaining clocks
X1_25
X2_25
XTAL
CPU PLL
(SPREAD
CAPABLE)
25MHz(1:0)
CPUCLK
VttPwr_GD/PD#
OE_CPU
OE_96
OE_RMIIA
OE_RMIIB
SMBADR
SMBDAT
SMBCLK
CONTROL
LOGIC
DOT PLL
(SPREAD
CAPABLE)
FIXED
PLL
DIVIDERS
8
DIVIDERS
DOT96SS
33.33MHz
RMII(7:0)
32.768KHz
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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9FGP202A
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9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Truth Table 1: VttPwr_GD/PD# and OE_96
V ttPwr_ GD/ PD#
Pin 40
0
0
1
1
OE_96
Pin 5
0
1
0
1
Clocks
All clocks are powered down
All clocks are powered down
All clocks are enabled except DOT96SS
*All clocks are enabled including DOT96SS
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
Truth Table 2: VttPwr_GD/PD# and OE_CPU
V ttPwr_ GD/ PD#
Pin 40
0
0
1
1
OE_ CPU
Pin 6
0
1
0
1
Clocks
All clocks are powered down
All clocks are powered down
All clocks are enabled except CPUCLK
*All clocks are enabled including CPUCLK
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Table 1: CPU Spread and Frequency Selection
CPU
CPU
CPU
CPU
SS_EN
F S2
FS1
FS0 CPU
Byte 0
Byte 0
Byte 0
Byte 0
MH z
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
1
266.67
133.33
0 0 1 0 200.00
0 0 1 1 166.67
0 1 0 0 333.33
0 1 0 1 100.00
0 1 1 0 400.00
0 1 1 1 200.00
1 0 0 0 266.67
1 0 0 1 133.33
1 0 1 0 200.00
1 0 1 1 166.67
1 1 0 0 333.33
1 1 0 1 100.00
1 1 1 0 400.00
1 1 1 1 200.00
Do wn
Spread %
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
5
9FGP202A
REV D 070511
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 9FGP202A electronic component. |
| Information | Total 19 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 9FGP202A.PDF Datasheet ] | |
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