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PDF 9FG1901H Data sheet ( Hoja de datos )
| Número de pieza | 9FG1901H | |
| Descripción | Frequency Generator | |
| Fabricantes | IDT | |
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Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
9FG1901H
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
•
•
•
•
•
•
•
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
• VDDA controlled power down mode
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#, 13
OE_01234#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1386A - 02/02/10
1 page  
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9FG1901 Programmable Gear Ratios
SMBus
Byte 0
Input Output Gear Ratio
(m) (n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0 266.7 320.0 333.3 400.0
00000 3
1
0.333 66.7 88.9 106.7 111.1 133.3
00001 5
2
0.400 80.0 106.7 128.0 133.3 160.0
0 0 0 1 0 12
5
0.417 83.3 111.1 133.3 138.9 166.7
00011 2
1
0.500 100.0 133.3 160.0 166.7 200.0
00100 5
3
0.600 120.0 160.0 192.0 200.0 240.0
00101 8
5
0.625 125.0 166.7 200.0 208.3 250.0
00110 3
2
0.667 133.3 177.8 213.3 222.2 266.7
00111 4
3
0.750 150.0 200.0 240.0 250.0 300.0
01000 6
5
0.833 166.7 222.2 266.7 277.8 333.3
01001 1
1
1.000 200.0 266.7 320.0 333.3 400.0
01010 5
6
1.200 240.0 320.0 384.0 400.0 NA
01011 4
5
1.250 250.0 333.3 400.0 NA NA
01100 3
4
1.333 266.7 355.6 NA
NA NA
01101 2
3
1.500 300.0 400.0 NA
NA NA
01110 3
5
1.667 333.3 NA NA NA NA
01111 1
2
2.000 400.0 NA NA NA NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33 160 166.67
10000 3
1
0.333
10001 5
2
0.400
NA 53.3 64.0 66.7
1 0 0 1 0 12
5
0.417
NA 55.6 66.7 69.4
10011 2
1
0.500 50.0 66.7 80.0 83.3
10100 5
3
0.600 60.0 80.0 96.0 100.0
10101 8
5
0.625 62.5 83.3 100.0 104.2
10110 3
2
0.667 66.7 88.9 106.7 111.1
10111 5
4
0.800 80.0 106.7 128.0 133.3
11000 6
5
0.833
NA 111.1 133.3 138.9
11001 1
1
1.000 100.0 133.3 160.0 166.7
11010 5
6
1.200 120.0 160.0 192.0 200.0
11011 4
5
1.250 125.0 166.7 200.0 208.3
11100 3
4
1.333 133.3 177.8 213.3 222.2
11101 2
3
1.500 150.0 200.0
11110 3
5
1.667 166.7 222.2 266.7 277.8
11111 1
2
2.000 200.0 266.7 320.0 333.3
Note: Lines in BOLD are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and device operation is not guaranteed
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
5
1386A - 02/02/10
5 Page 
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Human Body Model
GND - 0.5
GND - 0.5
-65
0
2000
VDD + 0.5V
VDD + 0.5V
150
70
115
V
V
°C
°C
°C
V
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
VIH
VIL
IIH
IIL1
VIH_FS
VIL_FS
IDD3.3OP
IDD3.3PD
Fi
Lpin
CIN
COUT
TSTAB
VMAX
VOL
IPULLUP
TRI2C
TFI2C
3.3 V +/-5%, Except CLK_IN
3.3 V +/-5%, Except CLK_IN
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
3.3 V +/-5%, Applies to
FS_A_410 pin
3.3 V +/-5%, Applies to
FS_A_410 pin
all outputs driven
all differential pairs tri-stated
VDD = 3.3 V
2
VSS - 0.3
-5
-5
0.7
VSS - 0.3
100
Logic Inputs
Output pin capacitance
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Maximum input voltage
@ IPULLUP
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
30
4
VDD + 0.3
0.8
5
V
V
uA
uA
1
1
VDD + 0.3 V
0.35 V
600 mA
36 mA
400 MHz
7 nH
6 pF
5 pF
1.8 ms
33 kHz
300 us
5 ns
5 ns
5.5 V
0.4 V
mA
1000
ns
300 ns
1
1
1
1
3
1
1
1
1
1
1
1
2
1
1
1
1
1
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
11
1386A - 02/02/10
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 9FG1901H.PDF ] | |
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