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8T74S208 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8T74S208
Beschreibung 2.5V Differential LVDS Clock Divider and Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 18 Seiten
8T74S208 Datasheet, Funktion
2.5V Differential LVDS Clock Divider
and Fanout Buffer
8T74S208
DATA SHEET
General Description
The 8T74S208 is a high-performance differential LVDS clock divider
and fanout buffer. The device is designed for the frequency division
and signal fanout of high-frequency, low phase-noise clocks. The
8T74S208 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8T74S208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. The
integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I2C register. On power-up, all outputs are
enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVDS outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enabled/ disabled by I2C interface
• Output skew: 45ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 96fs (typical)
• Full 2.5V supply voltage
• Outputs enabled at power up
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0] Pulldown (2)
2
SDA Pullup
SCL Pullup
ADR[1:0] Pulldown (2)
2
I2C
8
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
VDDO
 
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
8T74S208
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
VDDO
Q7 32-Lead VFQFN
nQ7 5mm x 5mm x 0.925mm
package body
NL Package, Top View
8T74S208 REVISION 1 09/10/14
1 ©2014 Integrated Device Technology, Inc.






8T74S208 Datasheet, Funktion
8T74S208 DATA SHEET
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input
fREF Frequency IN, nIN
fSCL I2C Clock Frequency
Buffer Additive Phase Jitter,
tJIT
RMS; refer to Additive Phase
fREF =156.25MHz,
Jitter Section, measured with Integration Range: 12kHz – 20MHz
FSEL[1:0] = 00
1 GHz
400 MHz
96 120 fs
FSEL[1:0] = 00
420
620 ps
tPD
Propagation IN, nIN to
Delay2
Qx, nQx
FSEL[1:0] = 01
FSEL[1:0] = 10
580
680
800 ps
920 ps
tsk(o)
Output Skew3, 4
FSEL[1:0] = 11
780
1050
45
ps
ps
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew4, 5, 6
FSEL[1:0] = 00
55 ps
200 ps
FSEL[1:0] = 00
50 %
odc Output Duty Cycle7
FSEL[1:0] = 01
FSEL[1:0] = 10
48 50 52 %
48 50 52 %
FSEL[1:0] = 11
48 50 52 %
Output Enable and Disable
Output Enable/ Disable State
tPDZ
Time8
from/ to Active/ Inactive
1 µs
tR / tF
Output Rise/ Fall Time
20% to 80%
10% to 90%
155 230 ps
245 350 ps
NOTE: 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE: 2. Measured from the differential input crosspoint to the differential output crosspoint.
NOTE: 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE: 4. This parameter is defined in accordance with JEDEC Standard 65.
NOTE: 5. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
NOTE: 6. Part-to-part skew specification does not guarantee divider synchronization among devices.
NOTE: 7. If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE: 8. Measured from SDA rising edge of I2C stop command.
2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER
6
REVISION 1 09/10/14

6 Page









8T74S208 pdf, datenblatt
8T74S208 DATA SHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100parallel resistor at the receiver and a 100differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 6A can be used
with either type of output structure. Figure 6B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
ZO ZT
Figure 6A. Standard LVDS Termination
LVDS
Driver
ZO ZT
Figure 6B. Optional LVDS Termination
ZT
LVDS
Receiver
ZT
2 LVDS
C
Receiver
ZT
2
2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER
12
REVISION 1 09/10/14

12 Page





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