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8SLVP2106 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8SLVP2106
Beschreibung LVPECL Output Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 24 Seiten
8SLVP2106 Datasheet, Funktion
Low Phase Noise, Dual 1-to-6, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2106
DATA SHEET
General Description
The 8SLVP2106 is a high-performance differential dual 1:6 LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2106 is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2106 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two independent buffers with six low skew outputs each are
available. The integrated bias voltage references enable easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QA5
nQA5
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
Features
Two 1:6, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 340ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: VCC = 3.3V)
Full 3.3V and 2.5V supply voltage modes
Maximum device current consumption (IEE): 114mA
Available in Lead-free (RoHS 6), 40-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Supports case temperature 105°C operations
Pin Assignment
30 29 28 27 26 25 24 23 22 21
VCC 31
QB2 32
nQB2 33
QB3 34
nQB3 35
QB4 36
nQB4 37
QB5 38
nQB5 39
VCC 40
8SLVP2106i
40-lead VFQFN
6mm x 6mm x 0.925mm package body
NL Package
Top View
1 2 3 4 5 6 7 8 9 10
20 VCC
19 nQA3
18 QA3
17 nQA2
16 QA2
15 nQA1
14 QA1
13 nQA0
12 QA0
11 VCC
8SLVP2106 REVISION B 6/9/15
1 ©2015 Integrated Device Technology, Inc.






8SLVP2106 Datasheet, Funktion
8SLVP2106 DATA SHEET
Table 4B. Buffer Additive Phase Jitter, tJIT, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 1kHz - 40MHz
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 10kHz - 20MHz
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 12kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 1kHz - 40MHz
tJIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 10kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 12kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 1kHz - 40MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 10kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 12kHz - 20MHz
Typical
98
61
61
63
46
46
54
42
42
Maximum Units
113 fs
81 fs
81 fs
74 fs
55 fs
54 fs
72 fs
55 fs
55 fs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when
the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Table 4C. Buffer Additive Phase Jitter, tJIT, 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 1kHz - 40MHz
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 10kHz - 20MHz
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 12kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 1kHz - 40MHz
tJIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz Square Wave, VPP = 1V
Integration Range: 10kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 12kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 1kHz - 40MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 10kHz - 20MHz
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 12kHz - 20MHz
Typical
103
64
64
66
48
48
58
45
45
Maximum Units
119 fs
85 fs
84 fs
79 fs
57 fs
57 fs
79 fs
60 fs
60 fs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.Additive Phase Jitter
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
6
REVISION B 6/9/15

6 Page









8SLVP2106 pdf, datenblatt
8SLVP2106 DATA SHEET
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. Both differential signals must meet the VPP and VCMR input
requirements. Figures 3A to 3C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
LVPECL
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3B. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
12
REVISION B 6/9/15

12 Page





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