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8P34S2102 Schematic ( PDF Datasheet ) - IDT

Teilenummer 8P34S2102
Beschreibung Dual 1:2 LVDS Output 1.8V Fanout Buffer
Hersteller IDT
Logo IDT Logo 




Gesamt 19 Seiten
8P34S2102 Datasheet, Funktion
Dual 1:2 LVDS Output 1.8V Fanout Buffer
8P34S2102
Datasheet
Description
The 8P34S2102 is a high-performance, low-power, differential
dual 1:2 LVDS output, 1.8V fanout buffer. The device is designed
for the fanout of high-frequency, very low additive phase-noise
clock and data signals. Two independent buffer channels are
available. Each channel has two low-skew outputs. High isolation
between channels minimizes noise coupling. AC characteristics
such as propagation delay are matched between channels.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8P34S2102 ideal for those clock distribution
applications demanding well-defined performance and
repeatability. The device is characterized to operate from a 1.8V
power supply. The integrated bias voltage references enable easy
interfacing of AC-coupled signals to the device inputs.
Block Diagram
Features
Dual 1:2 low skew, low additive jitter LVDS fanout buffers
Matched AC characteristics across both channels
High isolation between channels
Low power consumption
Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS
levels
Maximum input clock frequency: 2GHz
Output amplitudes: 350mV, 500mV (selectable)
Output bank skew: 8ps typical
Output skew: 10ps typical
Low additive phase jitter, RMS: 45fs typical
(fREF = 156.25MHz, 12kHz - 20MHz)
Full 1.8V supply voltage mode
Device current consumption (IDD): 76mA typical
Lead-free (RoHS 6), 16-lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Supports case temperature up to 105°C
VDD
51k
CLKA
nCLKA
51k 51k
QA0
nQA0
QA1
nQA1
VREF
Voltage
Reference
VDD
51k
CLKB
nCLKB
51k 51k
VDD
51k
SELA
8P34S2102 transistor count: 293
QB0
nQB0
QB1
nQB1
©2016 Integrated Device Technology, Inc.
1
October 20, 2016






8P34S2102 Datasheet, Funktion
8P34S2102 Datasheet
AC Electrical Characteristics
Table 9. AC Electrical Characteristics, VDD = 1.8V ± 5%, TA = -40°C to 85°C [a]
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum
Units
fREF
V/t
tPD
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Input frequency
Input edge rate
Propagation delay[b], [c]
Output skew[d], [e]
Output bank skew[e], [f]
Pulse skew[g]
Part-to-part skew[e], [h]
CLKA to any QAx, CLKB to any nQBx
fREF = 100MHz
1.5
100 225
10
8
5
2 GHz
V/ns
400 ps
30 ps
25 ps
20 ps
200 ps
tJIT
N(30M)
Buffer Additive Phase
Jitter, RMS;
500mV amplitude;
refer to Additive Phase
Jitter
Clock single-side band
phase noise
tJIT, SP
Spurious suppression,
coupling between
channels
fREF = 156.25MHz;
Integration range: 1kHz – 40MHz
fREF = 156.25MHz square wave, VPP = 1V;
Integration range: 12kHz – 20MHz
30MHz offset from carrier and noise floor
fQA = 491.52MHz, fQB = 61.44MHz;
measured between neighboring outputs
fQA = 491.52MHz, fQB = 15.36MHz;
measured between neighboring outputs
60
45
< -160
-71
-82
75 fs
55 fs
dBc/Hz
dB
dB
tR / tF
VPP
VPP_DIFF
VCMR
VOD
VOS
Output rise/ fall time
Input voltage CLKA,
amplitude
CLKB
Differential
input voltage
amplitude
CLKA,
CLKB
Common mode
input voltage[i]
Differential
output voltage
Offset voltage
10% to 90%, outputs loaded with 100
20% to 80%, outputs loaded with 100
SELA = 0, outputs loaded with 100
SELA = 1, outputs loaded with 100
SELA = 0
SELA = 1
220
110
0.15
0.3
400
250
1.2
2.4
ps
ps
V
V
1.1
VDD – (VPP/2)
V
247 350 454 mV
300 500 650 mV
0.77 V
0.68 V
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
[b] Measured from the differential input crossing point to the differential output crossing point.
[c] Input VPP = 400mV.
[d] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
©2016 Integrated Device Technology, Inc.
6
October 20, 2016

6 Page









8P34S2102 pdf, datenblatt
8P34S2102 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90and 132. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS
compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown
in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional
termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a
non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In
addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for
compatibility with the output.
Figure 7. Standard LVDS Termination
LVDS
Driver
ZO ZT
ZT
LVDS
Receiver
Figure 8. Optional LVDS Termination
LVDS
Driver
ZO ZT
ZT
2 LVDS
C
Receiver
ZT
2
©2016 Integrated Device Technology, Inc.
12
October 20, 2016

12 Page





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