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PDF MCP39F521 Data sheet ( Hoja de datos )
| Número de pieza | MCP39F521 | |
| Descripción | I2C Power Monitor | |
| Fabricantes | Microchip | |
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MCP39F521
I2C Power Monitor with Calculation and Energy Accumulation
Features
• Power Monitoring Accuracy Capable of 0.1%
Error Across 4000:1 Dynamic Range
• Built-In Calculations on Fast 16-bit Processing
Core
- Active, Reactive, Apparent Power
- True Root Mean Square (RMS) Current,
RMS Voltage
- Line Frequency, Power Factor
• 64-bit Wide Import and Export Active Energy
Accumulation Registers
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers
• Signed Active and Reactive Power Outputs
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 100 µs Latency
• Automatic Event Pin Control through Fast Voltage
Surge Detection, Less than 5 ms Delay
• I2C Interface, up to 400 kHz Clock Rate
• Two Independent Registers for Minimum and
Maximum Output Quantity Tracking
• Fast Calibration Routines and Simplified
Command Protocol
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
• Low-Drift Internal Voltage Reference,
10 ppm/°C Typical
• 28-lead 5 x 5 mm QFN Package
• Extended Temperature Range -40°C to +125°C
Applications
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
• Real-Time Measurement of Input Power for
AC/DC Supplies
• Intelligent Power Distribution Units
Description
The MCP39F521 is a highly integrated, complete
single-phase power-monitoring device, designed for
real-time measurement of input power for AC/DC
power supplies, power distribution units, consumer and
industrial applications. It includes dual-channel
delta-sigma ADCs, a 16-bit calculation engine,
EEPROM and a flexible two-wire I2C interface.
An integrated low-drift voltage reference with
10 ppm/°C in addition to 94.5 dB of signal-to-noise and
distortion ratio (SINAD) performance on each
measurement channel allows for better than 0.1%
accurate designs across a 4000:1 dynamic range.
Package Types
MCP39F521
5x5 QFN*
28 27 26 25 24 23 22
EVENT 1
21 AGND
NC 2
20 AN_IN
NC 3
COMMONB 4
COMMONA 5
19 V1+
EP
29
18 V1-
17 I1-
OSCI 6
16 I1+
OSCO 7
15 A1
8 9 10 11 12 13 14
*Includes Exposed Thermal Pad (EP); see Table 3-1.
2015 Microchip Technology Inc.
DS20005442A-page 1
1 page  
MCP39F521
TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V, TA = -40°C
to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Calibration, Calculation and Event Detection Times
Auto-Calibration Time
tCAL
— 2N x (1/fLINE)
Minimum Time
for Voltage Surge/Sag
tAC_SASU
— see
Section 7.0
Detection
—
—
ms Note 3
ms Note 4
24-Bit Delta-Sigma ADC Performance
Analog Input
Absolute Voltage
VIN
-1
— +1 V
Analog Input
Leakage Current
Differential Input
Voltage Range
Offset Error
Offset Error Drift
AIN —
(I1+ – I1-),
(V1+ – V1-)
VOS
-600/GAIN
-1
—
1 — nA
— +600/GAIN mV VREF = 1.2V,
proportional to VREF
— +1 mV
0.5 — µV/°C
Gain Error
Gain Error Drift
GE -4
— +4 % Note 5
— 1 — ppm/°C
Differential Input
Impedance
Signal-to-Noise
and Distortion Ratio
ZIN
SINAD
232
142
72
38
36
33
92
—
—
—
—
—
—
94.5
— k G = 1
— k G = 2
— k G = 4
— k G = 8
— k G = 16
— k G = 32
— dB Note 6
Total Harmonic Distortion
Signal-to-Noise Ratio
Spurious Free
Dynamic Range
Crosstalk
THD
SNR
SFDR
CTALK
—
92
—
—
-106.5
95
111
-122
-103
—
—
—
dBc Note 6
dB Note 6
dB Note 6
dB
AC Power
AC PSRR
—
-73
— dB AVDD and
Supply Rejection Ratio
DVDD = 3.3V + 0.6VPP,
100 Hz, 120 Hz, 1 kHz
DC Power
Supply Rejection Ratio
DC Common
Mode Rejection Ratio
DC PSRR
DC CMRR
—
—
-73
-105
— dB AVDD and DVDD = 3 to
3.6V
— dB VCM varies
from -1V to +1V
Note 1:
2:
3:
4:
5:
6:
7:
Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 4 line cycles.
Specification by design and characterization; not production tested.
N = Value in the Accumulation Interval Parameter register. The default value of this register is 2 or
TCAL = 80 ms for 50 Hz line.
Applies to Voltage Sag and Voltage Surge events only.
Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0, Typical
Performance Curves for typical performance.
VIN = 1VPP = 353 mVRMS @ 50/60 Hz.
Variation applies to internal clock and I2C only. All calculated output quantities are temperature
compensated to the performance listed in the respective specification.
2015 Microchip Technology Inc.
DS20005442A-page 5
5 Page 
MCP39F521
3.0 PIN DESCRIPTION
The description of the pins are listed in Table 3-1.
TABLE 3-1:
MCP39F521
5x5 QFN
1
2, 3, 8, 9
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24, 27
25
26
28
29
PIN FUNCTION TABLE
Symbol
Function
EVENT
NC
COMMONB
COMMONA
OSCI
OSCO
RESET
AVDD
A0
SCL
SDA
A1
I1+
I1-
V1-
V1+
AN_IN
AGND
ZCD
REFIN+/OUT
DGND
DVDD
MCLR
DR
EP
Event Output Pin
No Connect (must be left floating)
Common pin B, to be connected to COMMONA
Common pin A, to be connected to COMMONB
Oscillator Crystal Connection Pin or External Clock Input Pin
Oscillator Crystal Connection Pin
Reset Pin for Delta Sigma ADCs
Analog Power Supply Pin
I2C Address Select Pin A0
I2C Serial Clock
I2C Serial Data
I2C Address Select Pin A1
Noninverting Current Channel Input for 24-bit ADC
Inverting Current Channel Input for 24-bit ADC
Inverting Voltage Channel Input for 24-bit ADC
Noninverting Voltage Channel Input for 24-bit ADC
Analog Input for SAR ADC
Analog Ground Pin, Return Path for internal analog circuitry
Zero Crossing Detection Output
Noninverting Voltage Reference Input and Internal Reference Output Pin
Digital Ground Pin, Return Path for internal digital circuitry
Digital Power Supply Pin
Master Clear for Device
Data Ready (must be left floating)
Exposed Thermal Pad (to be connected to DGND)
3.1 Event Output Pin (EVENT)
This digital output pin can be configured to act as an
output flag based on various internal raise conditions.
Control is modified through the Event Configuration
register.
3.2 Common Pins (COMMONA and
COMMONB)
The COMMONA and COMMONB pins are internal
connections for the MCP39F521. These two pins
should be connected together in the application.
3.3 Oscillator Pins (OSCI/OSCO)
OSCI and OSCO provide the master clock for the
device. Appropriate load capacitance should be
connected to these pins for proper operation. An
optional 4 MHz crystal can be connected to these pins.
If a crystal of external clock source is not detected, the
device will clock from the internal 4 MHz oscillator.
3.4 Reset Pin (RESET)
This pin is active-low and places the delta-sigma
ADCs, PGA, internal VREF and other blocks associated
with the analog front-end in a Reset state when pulled
low. This input is Schmitt-triggered.
2015 Microchip Technology Inc.
DS20005442A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP39F521.PDF ] | |
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