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BD11670GWL Schematic ( PDF Datasheet ) - ROHM Semiconductor

Teilenummer BD11670GWL
Beschreibung USB Switch IC
Hersteller ROHM Semiconductor
Logo ROHM Semiconductor Logo 




Gesamt 16 Seiten
BD11670GWL Datasheet, Funktion
USB Switch IC
DPDT Type
(Double Pole Double Throw)
BD11670GWL
General Description
BD11670GWL is a DPDT analog switch that supports
USB2.0 high-speed and has both a low resistance and a
low capacitance.
It supports input of dual power supplies from VBUS and
VCC. VBUS of up to 28V is supported.
All terminals have electrostatic discharge protection
circuit built-in.
Features
Dual Power-Supply Architecture, VCC and VBUS.
Power Supply Range (VBUS) : 3.8V to 28V.
Power Supply Range (VCC) : 3.0V to 5.5V.
5Ωswitches between the input and the output.
Low Capacity 2ch Analog SW.
Applications
Mobile phones, Tablet PC, Digital Still Cameras, Digital
Video Camcorders, Potable Navigation Devices, TV,
Portable DVD Players, Portable Game Systems,
Personal Computers, PDA,
Key Specifications
Power Supply Range (VCC):
Power Supply Range (VBUS):
Switch ON Resistance:
Operating Temperature Range:
3.0V to 5.5V
3.8V to 28V
5Ω(Typ)
-40°C to +85°C
Package(s)
WLCSP
W(Typ) x D(Typ) x H(Max)
1.20mm x 1.60mm x 0.57mm
UCSP50L1C
Typical Application Circuit
CVCC
1uF
VSYS or
VBAT CVBUS
1uF
VBUS
CVCCIN
0.1uF
VCC
VBUS
VCCIN
PMIC
USB_X
USB_Y
Selector
signal
UNC1_X
UNC2_X
UNC1_Y
UNC2_Y
SEL
GND
COM1
COM2
Figure 1. Application circuit
Product structure : Silicon monolithic integrated circuit
.www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 14 • 001
This product was not designed with protection against radioactive rays
1/12
TSZ02201-0232AH300120-1-2
15.Feb.2016 Rev.003






BD11670GWL Datasheet, Funktion
BD11670GWL
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.0
Ta=105
Ta=25
Ta=-60
1.0 2.0 3.0
V_UNC1_X [V]
VCC=5V
SEL=0V
COM1=-10mA
UNC1_X=0V→
7V
4.0
5.0
Figure 8. Ron vs Voltage
2.0
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
0.0
Ta=105
Ta=25
Ta=-60
VCC=5V
SEL=2V
COM1=0V
UNC1_X=05
V
1.0 2.0 3.0 4.0 5.0
V_UNC1_X [V]
Figure 9.Leak Current vs Input Voltage
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
6/12
TSZ02201-0232AH300120-1-2
15.Feb.2016 Rev.003

6 Page









BD11670GWL pdf, datenblatt
BD11670GWL
Operational Notes continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin A
Pin B
C
B
E
Pin B
P+
NN
Parasitic
Elements
P P+
NN
P Substrate
GND
Parasitic
Elements
N P+
N P N P+ N
P Substrate
Parasitic
GND GND
Elements
Figure xx. Example of monolithic IC structure
B
N Region
close-by
C
E
Parasitic
Elements
GND
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
14. Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and power dissipation are all within the Area of Safe
Operation (ASO).
15. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always be
within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below the
TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat
damage.
16. Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
17. Disturbance light
In a device where a portion of silicon is exposed to light such as in a WL-CSP, IC characteristics may be affected due
to photoelectric effect. For this reason, it is recommended to come up with countermeasures that will prevent the chip
from being exposed to light.
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
12/12
TSZ02201-0232AH300120-1-2
15.Feb.2016 Rev.003

12 Page





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