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Teilenummer | NB100LVEP91 |
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Beschreibung | 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 11 Seiten NB100LVEP91
2.5 V/3.3 V Any Level
Positive Input to
-2.5 V/-3.3 V LVNECL
Output Translator
Description
The NB100LVEP91 is a triple any level positive input to NECL
output translator. The device accepts LVPECL, LVTTL, LVCMOS,
HSTL, CML or LVDS signals, and translates them to differential
LVNECL output signals (−2.5 V / −3.3 V).
To accomplish the level translation the LVEP91 requires three
power rails. The VCC pins should be connected to the positive power
supply, and the VEE pin should be connected to the negative power
supply. The GND pins are connected to the system ground plane. Both
VEE and VCC should be bypassed to ground via 0.01 mF capacitors.
Under open input conditions, the D input will be biased at VCC/2
and the D input will be pulled to GND. These conditions will force the
Q outputs to a low state, and Q outputs to a high state, which will
ensure stability.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
• Maximum Input Clock Frequency > 2.0 GHz Typical
• Maximum Input Data Rate > 2.0 Gb/s Typical
• 500 ps Typical Propagation Delay
• Operating Range:
♦ VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V
• Q Output will Default LOW with Inputs Open or at GND
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
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20
1
SOIC−20 WB
DW SUFFIX
CASE 751D−05
24 1
QFN−24
MN SUFFIX
CASE 485L−01
MARKING DIAGRAMS*
20
NB100LVEP91
AWLYYWWG
1
24
1 N100
VP91
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package
Shipping†
MB100LVEP91DWG
SOIC−20 WB 38 Units/Tube
(Pb-Free)
MB100LVEP91DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
MB100LVEP91MNG
QFN−24
(Pb-Free)
92 Units/Tube
MB100LVEP91MNR2G
QFN−24 3000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 19
1
Publication Order Number:
NB100LVEP91/D
NB100LVEP91
Table 7. AC CHARACTERISTICS (VCC = 2.375 V to 3.8 V; VEE = −2.375 V to −3.8 V; GND = 0 V)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP
Output Voltage Amplitude (Figure 4) (Note 1)
finĂV 1.0 GHz
finĂV 1.5 GHz
finĂV 2.0 GHz
575 800
525 750
300 600
600 800
525 750
250 550
550 800
400 750
150 500
mV
tPLH
tPHL0
Propagation Delay
Differential
D to Q
Single-Ended
ps
375 500 600 375 500 600 400 550 650
300 450 650 300 450 675 300 500 750
tSKEW
Pulse Skew (Note 2)
Output-to-Output (Note 3)
Part-to-Part (Diff) (Note 3)
15 75
25 95
50 125
15 75
30 105
50 125
15 80 ps
30 105
70 150
tJITTER
VINPP
RMS Random Clock Jitter (Note 4)
fin = 2.0 GHz
Peak-to-Peak Data Dependant Jitter (Note 5)
fin = 2.0 Gb/s
Input Voltage Swing (Differential Configuration)
(Note 6)
0.5 2.0
0.5 2.0
ps
0.5 2.0
20 20 20
200 800 1200 200 800 1200 200 800 1200 mV
tr, tf Output Rise/Fall Times @ 50 MHz
(20% − 80%) Q, Q
75 150 250 75 150 250 75 150 275 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND − 2.0 V. Input edge rates 150 ps (20% − 80%).
2. Pulse Skew = |tPLH − tPHL|
3. Skews are valid across specified voltage range, part-to-part skew is for a given temperature.
4. RMS Jitter with 50% Duty Cycle Input Clock Signal.
5. Peak-to-Peak Jitter with input NRZ PRBS 231−1 at 2.0 Gb/s.
6. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of ≈ 50.
850
750
650
550
450
350
250
0.5
AMP
RMS JITTER
1.0 1.5
2.0
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
2.5
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
www.onsemi.com
6
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ NB100LVEP91 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
NB100LVEP91 | 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator | ON Semiconductor |
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