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PDF AOZ8005 Data sheet ( Hoja de datos )
| Número de pieza | AOZ8005 | |
| Descripción | Ultra-Low Capacitance TVS Diode Array | |
| Fabricantes | Alpha & Omega Semiconductors | |
| Logotipo |  |
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AOZ8005
Ultra-Low Capacitance TVS Diode Array
General Description
The AOZ8005 is a transient voltage suppressor array
designed to protect high speed data lines such as HDMI
and Gigabit Ethernet from damaging ESD events.
This device incorporates eight surge rated, low capaci-
tance steering diodes and a TVS in a single package.
During transient conditions, the steering diodes direct the
transient to either the positive side of the power supply
line or to ground.
The AOZ8005 provides a typical line to line capacitance
of 0.47pF and low insertion loss up to 2GHz providing
greater signal integrity making it ideally suited for HDMI
1.3 applications, such as Digital TVs, DVD players,
set-top boxes and mobile computing devices.
The AOZ8005 comes in tiny SOT-23-6 and MSOP-10
packages and is rated -40°C to +85°C junction tempera-
ture range.
The MSOP package features a flow through layout
design.
Features
● ESD protection for high-speed data lines:
– IEC 61000-4-2, level 4 (ESD) immunity test
– ±15kV (air discharge) and ±8kV (contact discharge)
– Human Body Model (HBM) ±15kV
● Array of surge rated diodes with internal TVS diode
● Small package saves board space
● Protects four I/O lines
● Low capacitance between I/O lines: 0.47pF
● Low clamping voltage
● Low operating voltage: 5.0V
Applications
● HDMI ports
● Monitors and flat panel displays
● Set-top box
● USB 2.0 power and data line protection
● Video graphics cards
● Digital Video Interface (DVI)
● 10/100/1000 Ethernet
● Notebook computers
Typical Application
AOZ8005
AOZ8005
TX2+
TX2-
TX1+
HDMI TX1-
Transmitter
TX0+
TX0-
CLK+
CLK-
Connector Connector
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
HDMI
Receiver
CLK+
CLK-
Rev. 2.5 December 2009
AOZ8005
Figure 1. HDMI Ports
www.aosmd.com
AOZ8005
Page 1 of 14
1 page  
AOZ8005
Application Information
The AOZ8005 TVS is design to protect four high speed
data lines from ESD and transient over-voltage by
clamping them to a fixed voltage. When the voltages on
the protected lines exceed the limit, the internal steering
diode are forward bias will conduct the harmful transient
away from the sensitive circuitry. As system frequency
increase, printed circuit board layout becomes more
complex. A successful high speed board must integrate
the device and traces while avoiding signal transmission
problems associated with HDMI data speed.
High Speed HDMI PCB Layout Guidelines
Printed circuit board layout is the key to achieving the
highest level of surge immunity on power and data lines.
The location of the protection devices on the PCB is the
simplest and most important design rule to follow. The
AOZ8005 devices should be located as close as possible
to the noise source. The placement of the AOZ8005
devices should be used on all data and power lines that
enter or exit the PCB at the I/O connector. In most
systems, surge pulses occur on data and power lines
that enter the PCB through the I/O connector. Placing the
AOZ8005 devices as close as possible to the noise
source ensures that a surge voltage will be clamped
before the pulse can be coupled into adjacent PCB
traces. In addition, the PCB should use the shortest
possible traces. A short trace length equates to low
impedance, which ensures that the surge energy will be
dissipated by the AOZ8005 device. Long signal traces
will act as antennas to receive energy from fields that are
produced by the ESD pulse. By keeping line lengths as
short as possible, the efficiency of the line to act as an
antenna for ESD related fields is reduced. Minimize inter-
connecting line lengths by placing devices with the most
interconnect as close together as possible. The protec-
tion circuits should shunt the surge voltage to either the
reference or chassis ground. Shunting the surge voltage
directly to the IC’s signal ground can cause ground
bounce. The clamping performance of TVS diodes on a
single ground PCB can be improved by minimizing the
impedance with relatively short and wide ground traces.
The PCB layout and IC package parasitic inductances
can cause significant overshoot to the TVS’s clamping
voltage. The inductance of the PCB can be reduced by
using short trace lengths and multiple layers with sepa-
rate ground and power planes. One effective method to
minimize loop problems is to incorporate a ground plane
in the PCB design.
The AOZ8005 ultra-low capacitance TVS is designed to
protect four high speed data transmission lines from
transient over-voltages by clamping them to a fixed refer-
ence. The low inductance and construction minimizes
voltage overshoot during high current surges. When the
voltage on the protected line exceeds the reference
voltage the internal steering diodes are forward biased,
conducting the transient current away from the sensitive
circuitry. The AOZ8005 is designed for the ease of PCB
layout by allowing the traces to run underneath the
device. The pinout of the AOZ8005 is design to simply
drop onto the IO lines of a High Definition Multimedia
Interface (HDMI) design without having to divert the
signal lines that may add more parasitic inductance.
Pins 1, 2, 4 and 5 are connected to the internal TVS
devices and pins 6, 7, 9 and 10 are no connects. The
no connects was done so the package can be securely
soldered onto the PCB surface. See Figure 2.
CH 1
CH 2
VN
CH 3
CH 4
CH 1
CH 2
VP
CH 3
CH 4
Figure 2. Flow through Layout for two Line Pair
It is crucial that the layout is successful for a HDMI
design PCB board. Some of the problems associated
with high speed design are matching impedance of the
traces and to minimize the crosstalk between parallel
traces. This application note is to provide you as much
information to successfully design a high speed PCB
using Alpha & Omega devices.
The HDMI video signals are transmitted on a very high
speed pair of traces and any amount of capacitance,
inductance or even bends in a trace can cause the
impedance of a differential pair to drop as much as 40Ω.
This is not desirable because HDMI ports must maintain
a 100Ω ±15% on each of the four pairs of its differential
lines per HDMI Compliance Test Specifications. The
HDMI CTS specifies that the impedance on the differen-
tial pair of a receiver must be measured using a Time
Domain Reflectometry method with a pulse rise time of
≤200pS. The TDR measurements of the PCB traces
allows to locate and model discontinuities cause by the
geometrical features of a bend and by the frequency-
dependant losses of the trace itself. These fast edge
rates can contribute to noise and crosstalk, depending on
the traces and PCB dielectric construction material.
Rev. 2.5 December 2009
www.aosmd.com
Page 5 of 14
5 Page 
AOZ8005
Tape and Reel Dimensions, SOT23-5&6L
Tape
P1
K0
B0
P2
D0
D1
E1
E2
E
P0 A0
Unit: mm
Package
SOT23-5/6L
LP
A0
3.15
±0.10
B0
3.20
±0.10
K0 D0
D1
E
1.40 1.50
1.00
8.00
±0.10 ±0.05 +0.10 / -0 ±0.30
E1
1.75
±0.10
E2 P0
3.50 4.00
±0.05 ±0.10
Feeding Direction
P1 P2
4.00 2.00
±0.10 ±0.05
T
0.23
±0.03
Reel
J
W1
R
M
S
N
K
H
Unit: mm
Tape Size
8mm
Reel Size
ø177.8
M
ø177.8
Max.
N
55.0
Min.
W1 H
8.4 13.0
+1.50 / -0.0 +0.5 / -0.2
S
1.5
Min
KRJ
10.1
Min.
12.7
4.0
±0.1
Leader/Trailer and Orientation
Trailer Tape
300mm min.
Rev. 2.5 December 2009
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min.
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AOZ8005.PDF ] | |
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