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PDF 8T49N1012 Data sheet ( Hoja de datos )

Número de pieza 8T49N1012
Descripción Frequency Synthesizer
Fabricantes Integrated Device Technology　
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! 8T49N1012 Hoja de datos, Descripción, Manual

FemtoClock® NG 12-Output
Frequency Synthesizer
8T49N1012
Datasheet
General Description
The 8T49N1012 has one fractional-feedback PLL that can be used
for frequency synthesis. It is equipped with two integer and eight
fractional output dividers, allowing the generation of up to ten
different output frequencies, ranging from 8kHz to 1GHz. Eight of
these frequencies are completely independent of each other and the
inputs. Two more are related frequencies. The twelve outputs may
select among LVPECL, LVDS, HSCL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
synthesis application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates.
The device supports Output Enable inputs and Lock and LOS status
outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• Gigabit and Terabit IP switches / routers
• Wireless base station baseband
• Data communications
Features
• <350fs RMS typical jitter (including spurs), @122.88MHz (12kHz
to 20MHz)
• Operating modes: locked to input signal and free-run
• Operates from a 10MHz to 40MHz fundamental-mode crystal
• Accepts one LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input
clock
• Accepts frequencies ranging from 10MHz up to 600MHz
• Clock input monitoring
• Generates 12 LVPECL / LVDS / HSCL or 24 LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz (Q[8:11],
Differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Two Output Enable control inputs
• Lock and Loss-of-Signal status outputs
• Programmable output de-skew adjustments in steps as small as
16ps
• Register programmable through I2C or via external I2C EEPROM
• Bypass clock paths and Reference Output for system tests
• Power supply modes:
VCC
3.3V
/ VCCA
/ 3.3V
/
/
3V.C3CVO
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
• -40°C to 85°C ambient operating temperature
• Package: 72QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
October 28, 2016

1 page




8T49N1012 pdf
8T49N1012 Datasheet
Table 1. Pin Descriptions1 (Continued)
Number
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Name
VCCO3
nc
nQ2
Q2
VCCO2
nc
Rsvd
nc
nQ1
Q1
VCCO1
VCCO0
nQ0
Q0
nc
Type
Power
Unused
Output
Output
Power
Unused
Reserved Pulldown
Unused
Output
Output
Power
Power
Output
Output
Unused
54
PLL_BYP
Input
Pulldown
55 nQ5 Output
56 Q5 Output
57
VCCO5
Power
58
nRST
Input
Pullup
59 nQ4 Output
60 Q4 Output
61
VCCO4
Power
62
LOS
Output
63
VCCA
Power
64
CAP_REF
Analog
65
CAP
Analog
66
VCCA
Power
67
VCCA
Power
68
VCCA
Power
69
VCCCS
Power
70
CLK_SEL
Input
Pullup
Description
Output supply for Q3 output clock pair.
No internal connection.
Output Clock 2. Refer to the Output Drivers section for more details.
Output Clock 2. Refer to the Output Drivers section for more details.
Output supply for Q2 output clock pair.
No internal connection.
Reserved - leave unconnected.
No internal connection.
Output Clock 1. Refer to the Output Drivers section for more details.
Output Clock 1. Refer to the Output Drivers section for more details.
Output supply for Q1 output clock pair.
Output supply for Q0 output clock pair.
Output Clock 0. Refer to the Output Drivers section for more details.
Output Clock 0. Refer to the Output Drivers section for more details.
No internal connection.
Bypass Selection. Allow PLL references to bypass PLL and appear at Q[0:3].
LVTTL / LVCMOS interface levels.
Output Clock 5. Refer to the Output Drivers section for more details.
Output Clock 5. Refer to the Output Drivers section for more details.
Output supply for Q5 output clock pair.
Master Reset input. LVTTL / LVCMOS interface levels.
0 = All registers and state machines are reset to their default values
1 = Device runs normally
Output Clock 4. Refer to the Output Drivers section for more details.
Output Clock 4. Refer to the Output Drivers section for more details.
Output supply for Q4 output clock pair.
Loss of reference to PLL indicator. LVCMOS/LVTTL interface levels.
Core analog function supply voltage.
PLL External Capacitance reference.
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
Core analog function supply voltage.
Core analog function supply voltage.
Core analog function supply voltage.
Supply voltage for status and control signals: nRST, LOCK, LOS, PLL_BYP,
OE[1:0].
Clock select pin:
0: CLK, nCLK
1: XTAL (default)
©2016 Integrated Device Technology, Inc.
5
October 28, 2016

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8T49N1012 arduino
8T49N1012 Datasheet
I2C Master Mode
When operating in I2C mode, the 8T49N1012 has the capability to
become a bus master on the I2C bus for the purposes of reading its
configuration from an external I2C EEPROM. Only a block read cycle
will be supported.
As an I2C bus master, the 8T49N1012 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (B4h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I2C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N1012 will not support the following functions:
• I2C General Call
• Slave clock stretching
• I2C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I2C devices including the external EEPROM
used for booting
Sequential Read (1‐byte offset address)
S Dev Addr + W A
Offset Addr
A Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n A P
Sequential Read (2‐byte offset address)
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = none acknowledge
P = stop
Figure 4. I2C Master Read Cycle Sequencing
A Data n A P
©2016 Integrated Device Technology, Inc.
11
October 28, 2016

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