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NB3L8504S Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3L8504S
Beschreibung 2.5V / 3.3V 1:4 Differential Input to LVDS Fanout Buffer / Translator
Hersteller ON Semiconductor
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Gesamt 11 Seiten
NB3L8504S Datasheet, Funktion
NB3L8504S
2.5 V / 3.3 V 1:4 Differential
Input to LVDS Fanout Buffer
/ Translator
Description
The NB3L8504S is a differential 1:4 LVDS fanout buffer/translator
with OE control for each differential output. The differential inputs
which can be driven by either a differential or single−ended input, can
accept various logic level standards such as LVPECL, LVDS, HSTL,
HCSL and SSTL. These signals are then translated to four identical
LVDS copies of the input up to 700 MHz. As such, the NB3L8504S is
ideal for Clock distribution applications that require low skew.
The NB3L8504S is offered in the TSSOP−16 package.
Features
Four Differential LVDS Outputs
Each Differential Output has OE Control
700 MHz Maximum Output Frequency
660 ps Max Output Rise and Fall Times, LVCMOS
Translates Differential Input to LVDS Levels
Additive Phase Jitter RMS: < 100 fs Typical
50 ps Maximum Output Skew
350 ps Maximum Part−to−part Skew
1.3 ns Maximum Propagation Delay
Operating Range: VCC = 2.5 V ± 5% or 3.3 V ± 10%
−40°C to +85°C Ambient Operating Temperature
16−Pin TSSOP, 4.4 mm x 5.0 mm x 0.925 mm
These are Pb−Free Devices
Applications
Telecom
Ethernet
Networking
SONET
www.onsemi.com
MARKING
DIAGRAM*
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
NB3L
8504
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
CLK
CLK
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 2
1
Publication Order Number:
NB3L8504S/D






NB3L8504S Datasheet, Funktion
NB3L8504S
Figure 4. Additive Phase Jitter
Figure 5. Differential Inputs
Driven Differentially
VDD
VIHCMRmax
VIHCMR
VIHCMRmin
IN
IN
GND
VIHDmax
VILDmax
VID = VIHD - VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Figure 7. VIHCMR Diagram
Figure 6. Differential Inputs
Driven Differentially
Figure 8. Output−to−Output Skew
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