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PDF PN25F08 Data sheet ( Hoja de datos )
| Número de pieza | PN25F08 | |
| Descripción | 8M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | PARAGON | |
| Logotipo |  |
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SPI NOR
PN25F08
PN25F08
8M-BIT SERIAL FLASH MEMORY
Datasheet
Aug. 2015
A 1.4
NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION IS SUBJECT TO CHANGE AT
ANYTIME WITHOUT NOTICE, ALL PRODUCT SPECIFICATIONS ARE PROVIDED FOR
REFERENCE ONLY.TO ANY INTELLECTUAL, PROPERTY RIGHTS IN PARAGON
TECHNOLOGY LIMITED. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED.
www.paragontech.cn
A 1.4
1 page  
SPI NOR
PN25F08
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and
data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the
falling edge of SCK).
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the
serial SCK clock signal.
SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and
data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the
falling edge of SCK).
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0]
and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any
alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by
the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data
modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in
Status Register 2 (SR2[1]=1).
The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be
programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of
SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the
host system if not used for Quad mode.
HOLD (/HOLD)/IO3
The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of
write status register, programming, or erasing in progress.The operation of HOLD, need /CS keep low, and starts on
falling edge of the /HOLD signal, with CLK signal being low (if CLK is not being low, HOLD operation will not start
until CLK being low). The HOLD condition ends on rising edge of /HOLD signal with CLK being low (If CLK is not being
low, HOLD operation will not end until CLK being low).
The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with SCK being
at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold
condition starts whenever the SCK signal reaches the logic low state. Taking the /HOLD signal to the logic low state
does not terminate any Write, Program or Erase operation that is currently in progress.
VCC Power Supply
VCC is the supply voltage. is the single voltage used for all device functions including read, program, and erase.
VSS Ground
VSS is the reference for the VCC supply voltage.
A 1.4
5 Page 
4. SRP1,SRP0 bits
SPI NOR
PN25F08
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP
bits control the method of write protection: software protection, hardware protection, power supply lock-down
or one time programmable protection.
9.1.1.1 QEbit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and
IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or
/HOLD pins directly to the power supply or ground).
9.4.2.6 LB3/LB2/LB1Bit
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and
status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte
Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1.
9.4.2.7 CMPbit
The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-BP0 bits
to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for
details. The default setting is CMP=0.
9.4.2.8 SUSbit
The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend
(75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down,
power-up cycle.
A 1.4
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PN25F08.PDF ] | |
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