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PDF ML620Q136 Data sheet ( Hoja de datos )
| Número de pieza | ML620Q136 | |
| Descripción | 16-bit micro controller | |
| Fabricantes | LAPIS | |
| Logotipo |  |
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ML620Q131/2/3/4/5/6
16-bit micro controller
FEDL620Q130-02
Issue Date: May 12, 2016
GENERAL DESCRIPTION
This LSI is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with rich
peripheral functions such as the timer, PWM, comparator, voltage level supervisor, UART, I2C, and successive approximation
type A/D converter.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipeline architecture
parallel processing. It has the data flash memory area which can be written by software.
In addition, the on-chip debug function that is installed enables software debugging and programming.
FEATURES
· CPU
- 16-bit RISC CPU (CPU name: nX-U16/100)
- Instruction system: 16-bit length instruction
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ On-chip debug function built in
‒ Minimum instruction execution time
30.5 μs (at 32.768 KHz system clock)
0.063 μs (at 16 MHz system clock)
· Internal memory
‒ Flash memory (program area) Rewrite count 100 cycles
ML620Q131: 8 Kbyte (4K x 16 bits)
ML620Q132: 16 Kbyte (8K x 16 bits)
ML620Q133: 24 Kbyte (12K x 16 bits)
ML620Q134: 8 Kbyte (4K x 16 bits)
ML620Q135: 16 Kbyte (8K x 16 bits)
ML620Q136: 24 Kbyte (12K x 16 bits)
‒ Flash memory (data area)
Rewrite count 10,000 cycles
2 Kbyte (1K x 16 bits)
‒ SRAM
2 Kbyte (2K x 8 bits)
· Interrupt controller
- Non-maskable interrupt source: 2 (Internal sources: BACK-UP CLOCK, WDT)
- Maskable interrupt sources: 30 (Internal sources: 25, External sources: 5)
- Four interrupt levels and masking function
· Time base counter
- Low-speed time base counter ´ 1 channel
· Watchdog timer
‒ Non-maskable interrupt and reset
(The first overflow generates an interrupt, and the second overflow generates a reset)
‒ Free running
‒ Overflow period: 4 types selectable (125 ms, 500 ms, 2 s, and 8 s at 32.768 kHz)
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1 page  
BLOCK DIAGRAM
ML620Q131/ML620Q132/ML620Q133 Block Diagram
“*” indicates the secondary, tertiary or quarternary function.
FEDL620Q130-02
ML620Q131/2/3/4/5/6
VDD
VSS
VDDL
RESET N
TEST0
TEST1_N
OSC0*
OSC1*
LSCLK*
OUTCLK*
AIN0 to AIN5*
CMP0P*
CMP0M*
CMP1P*
EPSW1 3
PSW
Timing
Controller
On-Chip
ICE
CPU (nX-U16/100)
GREG
0 15
ELR1 3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
Power
RAM
2Kbyte
RESET &
TEST
OSC
INT
1
SA-ADC
INT
1
Analog
Comparator
×2
INT
2
Interrupt
Controller
INT
1 WDT
INT
3 TBC
INT
2
VLS
INT
1
DME
ECSR1 3
DSR/CSR
PC
BUS
Controller
Program
Memory
(FLASH)
8/16/24Kbyte
INT
SSIOx1
1
INT
2 UART
INT
2
I2C
Master/Slave
INT
10
8bit Timer
×10
INT
1
PWM
SCK0*
SIN0*
SOUT0*
RXD0*
TXD0*
RXD1*
TXD1*
SDA0*
SCL0*
PWMC*
INT
5 GPIO
PA0 to PA2
PB0 to PB7
Figure 1-1 ML620Q131/ML620Q132/ML620Q133 Block Diagram
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5 Page 
FEDL620Q130-02
ML620Q131/2/3/4/5/6
PAD
No.
(16pin
SSOP)
PAD PAD
No. No.
(16pin (20pin
WQFN) TSSOP)
10 7 12
11 9 13
8 5 10
15 14 19
Primary function
Pin name I/O
Feature
PB4/
CMP0P
PB5/
RXD0/
CMP0M
PB6/
AIN4/
RXD1
PB7/
LED1/
AIN5/
DUTI
I/O port/
Comparator 0
I/O
Non-inverting
input
I/O port/
UART0
I/O reception/
Comparator 0
Inverting input
I/O port/
AD input 4/
I/O
UART1
reception
I/O port/
LED drive
I/O AD input 5/
DUTY
measurement
Secondary function
Pin name I/O
Feature
TXD1
UART1
O
transmission
OUTCLK O
High-speed
clock
output
LSCLK
O
Low-speed
clock
output
TXD1
UART1
O
transmission
Tertiary function
Pin name I/O Feature
TXD0
UART0
O transmis
sion
TMJ
OUT
Timer J
O
output
TMF
OUT
Timer F
O
output
SCL
I2C
I/O clock
I/O
Quartic function
Pin name
I/O
Feature
SIN0
SSIO
I
data input
SSIO
SCK0
I/O
clock I/O
SDA
I/O
I2C
data
I/O
PWMC
O PWMC output
11/33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML620Q136.PDF ] | |
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