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PDF MCD2926 Data sheet ( Hoja de datos )
| Número de pieza | MCD2926 | |
| Descripción | 18MHz-650MHz Dual Frequency Synthesizer | |
| Fabricantes | MC Devices | |
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MC Devices®
MCD2926
18MHz-650MHz Dual Frequency Synthesizer
General Description
The MCD2926 is a high performance dual
frequency synthesizer with high frequency prescaler
for RF operation frequency from 18MHz to
650MHz. The MCD2926 contains two dual
modulus prescalers, three programmable counters,
one crystal oscillator, two phase detectors and two
programmable charge pumps, one MCU serial
interface. The on-chip prescalers and dividers
consist of a completed phase-lock-loop (PLL),
which is combined with on board VCO and LPF.
Users can lock any targeted frequency by setting
proper division with an external MCU. It has been
proven that MCD2926 can work stably within the
range of -40 to +85 degrees.
Typical Applications
■ FRS, PCS, Cordless phones
■ Portable wireless systems and other wireless
■ communication systems
Features
■ Operating Frequency: 18MHz~650MHz
■ Operating Voltage Range: 2.2 ~ 5.5V (3.3V
Typical)
■ Operating Power Consumption:
Single channel: 7.5mA @3.3V
Dual channel: 14mA @3.3V
■ Power down Consumption: < 1uA
■ The reference crystal oscillator supports
4~25MHz crystal
■ Dual modulus prescaler: 64/66
■ No dead-zone PFD
■ Digital Lock Detect Signal: when loop locked, LD
outputs high level.
■ Programmable charge pump current: 200uA,
400uA, or 800uA
■ 0.35um CMOS process
■ Package: TSSOP-16
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Version History
Version Issued time
V1.0 Jun.18, 2006
V1.1 Sep.6, 2006
V1.2 Dec.1, 2008
V2.0 Mar 05, 2009
V2.5 April 26, 2010
Notes
First version created.
Update the test parameter.
Modify the format.
Add packaging process and Soldering temperature profile
Change the maximum voltage to 5.5V, remove 1600uA
chargepump option.
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516 Bld4, National Software Base, Kejizhong 2 Rd, Shenzhen Hi-Tech Park, Shenzhen, China
1 OF 18
Tel: (86-755)8618 5088
Fax: (86-755)8618 5000
1 page  
MC Devices®
1. Function Description
The MCD2926 is a dual frequency synthesizer
based on the PLL (phase-lock-loop) principle, it
consists of a high-accuracy crystal oscillator, two
phase/frequency detectors, two charge pumps, one
programmable reference frequency divider and two
programmable feedback frequency dividers. The
dual synthesizer 、 two external VCOs and two
passive loop filters consist of two completed
separated PLL. The targeted frequencies can be
phase and frequency locked through the PLL when
an external MCU properly programme the divide
ratio of the reference frequency divider and
feedback frequency divider.
1.3 Feedback Divider (N Counter)
The channel1 and channel2 N counters are clocked
by the small signal FIN1 and FIN2, respectively.
The input of FIN1 and FIN2 should be AC coupled
signal through external capacitors. FIN1 and FIN2
are biased at 0.6VDD. An N counter consists of a
5-bit swallow counter with a divide ratio 0<A<31
and a 12-bit pulse counter with a divide ratio
3<B<4095. In conjunction with the 64/66 prescaler,
the total divide ratio can range from 192 to 262142
on a feedback channel. For the proper operation of
the prescaler, the pulse counter division ratio B
should be always equal to or greater than the
swallow counter division ratio A. See the
programming description section for details.
1.1 Reference Oscillator
The reference frequency for PLL is obtained by two
methods. First method is to input an external clock to
OSCIN pin with OSCO pin tied to VDD. Second way is to
apply an external crystal and few capacitors across the
OSCI pin and OSCO pin. External capacitors C1, C2, C3
and C4 are required to set the proper crystal’s load
capacitance and oscillation frequency, local oscillation
signal is buffered and output through the BO pin which
can be applied to the 2nd mixer input.
Crystal mode
C4
Logic mode
OSCI
OSCO
C1
BO
1000pF
C3
C2
2'nd
mixer
OSCI
OSCO
1000pF
External
reference
clock
VDD
BO
2'nd
mixer
1000pF
1.2 Reference Divider (R Counter)
The reference divider provides reference frequency for
PFD, it includes a fixed 1/2 divider and a 12-bit
programmable divider. The 12-bit divider can program the
division ratio between 3 and 4095. Due to the fixed 1/2
divider, the total divide ratio for reference divider would
range from 6 to 8190. See the programming description
section for details.
1.4 Prescaler
The prescaler of MCD2926 consists of a
pre-amplifier, a CML (current mode logic) 1/2
divider and a CMOS 32/33 dual modulus divider.
The prescaler clocks the subsequent CMOS N
counter.
1.5 Phase/Frequency Detector (PFD)
The channel1 and channel2 phase/frequency
detectors (PFD) are driven by their respective N
counters and R counter. PFD compares frequency
and phase of two inputs from reference counter and
N counter, outputs control logic to charge pump.
The polarity of the pump-up or pump-down control
is programmable according to VCO characteristics.
The phase detector receives a feedback signal from
charge pump in order to eliminate dead zone.
1.6 Charge Pump
The charge pump pumps up or pumps down current from an
external loop filter is according to the polarity control of it’s
PFD outputs. The loop filter converts the charge into VCO’s
control voltage
The charge pump steers the charge pump output CP1 or
CP2 to VDD (pump-up) or GND (pump-down). Under
—————————————————————————————————————————————————————————————————————
516 Bld4, National Software Base, Kejizhong 2 Rd, Shenzhen Hi-Tech Park, Shenzhen, China
5 OF 18
Tel: (86-755)8618 5088
Fax: (86-755)8618 5000
5 Page 
MC Devices®
Divide ratio of the programmable 12bit counter:
Division ratio (R) R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3 0 0 0 000000011
4 0 0 0 000000100
● ● ● ● ●●●●●●●●●
4095
111
R = R1x20 + R2x2¹ + … + R12x211 (R≥3)
111111111
The total division ratio range: 6 to 8190
2.5 Programmable Channel 1 and Channel 2 N Counters
These programmable dividers are composed of a 5-bit swallow counter and a 12-bit pulse counter, in
conjunction with the 64/66 prescaler to provide divide ratio range from 192 to 262142.
2.5.1 Channel1 configuration word
LSB
MSB
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 GC2=1 GC1=0
|----swallow counter----|-------------------------------pulse counter------------------------|--group code-|
2.5.2 Channel2 configuration word
LSB
MSB
N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 GC2=0 GC1=1
|------swallow counter------|-------------------------------pulse counter------------------------------------| --group code---|
2.5.3 Swallow counter division ratio (A)
Division ratio (A) N5 N4 N3 N2 N1
0 00000
1 00001
● ●●●●●
31
A = N1x20 + N2x21 + … + N5x24
11111
Division ratio range: 0 to 31
2.5.4 Pulse counter divide ratio (B)
Division ratio (B) N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6
3 0 0 0 0 0 0 0 0 0011
4 0 0 0 0 0 0 0 0 0100
● ● ● ● ● ● ● ● ● ●●●●
4095
1 1 1 1 1 1 1 1 1111
B = N6x20 + N7x2¹ + … + N17x211
Division ratio range: 3 to 4095 (B≥A)
—————————————————————————————————————————————————————————————————————
516 Bld4, National Software Base, Kejizhong 2 Rd, Shenzhen Hi-Tech Park, Shenzhen, China
11 OF 18
Tel: (86-755)8618 5088
Fax: (86-755)8618 5000
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MCD2926.PDF ] | |
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