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PDF MR27V12850L Data sheet ( Hoja de datos )

Número de pieza MR27V12850L
Descripción P2ROM
Fabricantes LAPIS 
Logotipo LAPIS Logotipo



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MR27V12850L
P2ROM8M–Word × 16–Bit or 16M–Word × 8–Bit Page mode
FEDR27V12850L-002-02
Issue Date: Jan. 06, 2009
FEATURES
· 8,388,608-word × 16-bit/16,777,216-word × 8-bit electrically
switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6 V power supply
· Access time ..................... 85 ns MAX
· Page Access time ............ 30 ns MAX
· Operating current ............ 50 mA MAX(5MHz)
· Standby current ............... 10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR27V12850L-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory
with minimal effect on the production throughput. The cost
is included in the unit price.
· Custom Marking is available at no additional charge.
· Pin Compatible with Mask ROM
PIN CONFIGURATION (TOP VIEW)
BYTE# 1
A16 2
A15 3
A14 4
A13 5
A12 6
A11 7
A10 8
A9 9
A8 10
A19 11
A21 12
A20 13
A18 14
A17 15
A7 16
A6 17
A5 18
A4 19
A3 20
A2 21
A1 22
A0 23
CE# 24
48 Vss
47 Vss
46 D15/A–1
45 D7
44 D14
43 D6
42 D13
41 D5
40 D12
39 D4
38 VCC
37 VCC
36 A22
35 D11
34 D3
33 D10
32 D2
31 D9
30 D1
29 D8
28 D0
27 OE #
26 Vss
25 Vss
48TSOP(Type-I)
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1 page




MR27V12850L pdf
FEDR27V12850L-002-02
MR27V12850L / P2ROM
TIMING CHART (READ CYCLE)
RANDOM ACCESS MODE READ CYCLE
A0 to A22 (Word mode)
A-1 to A22 (Byte mode)
tC
tC
tCE
CE#
tACC
tOE
OE#
tACC
D0 to D15(Word mode)
D0 to D7(Byte mode)
Hi-Z
D8 to D15 : Hi-Z(Byte mode)
tOH
Valid Data
tOH
tCHZ
tOHZ
Valid Data
Hi-Z
PAGE ACCESS MODE READ CYCLE
A3 to A21
tC
A0 to A2 (Word mode)
A-1 to A2 (Byte mode)
CE#
OE#
D0 to D15(Word mode)
D0 to D7(Byte mode)
D8 to D15 : Hi-Z(Byte mode)
tCE
tOE
tACC
Hi-Z
tPC tPC
tOH
tPAC
tPAC
tCHZ
tOHZ
Hi-Z
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