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PDF CY7C135A Data sheet ( Hoja de datos )
| Número de pieza | CY7C135A | |
| Descripción | 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C135, CY7C135A
CY7C1342
4K x 8 Dual-Port Static RAM and 4K x 8
Dual-Port SRAM with Semaphores
Features
■ True dual-ported memory cells, which allow simultaneous
reads of the same memory location
■ 4K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: ICC = 160 mA (max)
■ Fully asynchronous operation
■ Automatic power down
■ Semaphores included on the 7C1342 to permit software
handshaking between ports
■ Available in 52-pin PLCC
■ Pb-free packages available
Logic Block Diagram
R/WL
CEL
OEL
Functional Description
The CY7C135/135A[1] and CY7C1342 are high speed CMOS 4K
x 8 dual-port static RAMs. The CY7C1342 includes semaphores
that provide a means to allocate portions of the dual-port RAM
or any shared resource. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
location in memory. Application areas include interpro-
cessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). The
CY7C135/135A is suited for those systems that do not require
on-chip arbitration or are intolerant of wait states. Therefore, the
user must be aware that simultaneous access to a location is
possible. Semaphores are offered on the CY7C1342 to assist in
arbitrating between ports. The semaphore logic is comprised of
eight shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates that
a shared resource is in use. An automatic power down feature is
controlled independently on each port by a chip enable (CE) pin
or SEM pin (CY7C1342 only).
The CY7C135/135A and CY7C1342 are available in 52-pin
PLCC.
R/WR
CER
OER
I/O7L
I/O0L
A11L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
I/O7R
I/O0R
A11R
A0R
(7C1342 only) SEML
CEL
OEL
R/WL
SEMAPHORE
ARBITRATION
(7C1342 only)
CER
OER
R/WR
(7C1342 only)
SEMR
Note
1. CY7C135 and CY7C135A are functionally identical
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06038 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 09, 2008
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CY7C135, CY7C135A
CY7C1342
Switching Characteristics Over the Operating Range[6]
Parameter
Description
7C135-15
7C1342-15
Min Max
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Output Hold From Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE[7,8,9]
tHZOE[7,8,9]
tLZCE[7,8,9]
tHZCE[7,8,9]
tPU[9]
tPD[9]
OE LOW to Data Valid
OE Low to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
Write Cycle
15
3
3
3
0
15
15
10
10
10
15
tWC Write Cycle Time
tSCE
CE LOW to Write End
tAW Address Setup to Write End
tHA Address Hold from Write End
tSA Address Setup to Write Start
tPWE
Write Pulse Width
tSD Data Setup to Write End
tHD Data Hold from Write End
tHZWE[8,9]
R/W LOW to High Z
tLZWE[8,9]
R/W HIGH to Low Z
tWDD[10]
Write Pulse to Data Delay
tDDD[10]
Write Data Valid to Read Data Valid
Semaphore Timing[11]
15
12
12
2
0
12
10
0
3
10
30
25
tSOP
SEM Flag Update Pulse
(OE or SEM)
10
tSWRD
tSPS
SEM Flag Write to Read Time
SEM Flag Contention Window
5
5
7C135-20
7C1342-20
Min Max
7C135-25
7C135A-25
7C1342-25
Min Max
20 25
20 25
33
20 25
13 15
33
13 15
33
13 15
00
20 25
20 25
15 20
15 20
22
00
15 20
13 15
00
13 15
33
40 50
30 30
10 10
55
55
7C135-35
7C1342-35
Min Max
35
35
3
35
20
3
20
3
20
0
35
35
30
30
2
0
25
15
0
20
3
60
35
15
5
5
7C135-55
7C1342-55
Min Max
55
55
3
55
25
3
25
3
25
0
55
55
50
50
2
0
50
25
0
25
3
70
40
15
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH
and 30 pF load capacitance.
7. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
8. Test conditions used are Load 3.
9. This parameter is guaranteed but not tested.
10. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 6.
11. Semaphore timing applies only to CY7C1342.
Document #: 38-06038 Rev. *D
Page 5 of 12
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CY7C135, CY7C135A
CY7C1342
Ordering Information
4K x8 Dual-Port SRAM
Speed
(ns)
15
20
25
35
55
Ordering Code
CY7C135–15JC
CY7C135-15JXC
CY7C135–20JC
CY7C135–25JC
CY7C135-25JXC
CY7C135A–25JI
CY7C135–25JXI
CY7C135–35JC
CY7C135–35JI
CY7C135–55JC
CY7C135–55JI
Package
Name
J69
J69
J69
J69
J69
J69
J69
J69
J69
J69
J69
Package Type
52-Pin Plastic Leaded Chip Carrier
52-Pin Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Pb-Free Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
52-Pin Plastic Leaded Chip Carrier
Package Diagram
Figure 11. 52-Pin Pb-Free Plastic Leaded Chip Carrier J69
Operating
Range
Commercial
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-06038 Rev. *D
51-85004-*A
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CY7C135A.PDF ] | |
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