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LC717A10AJ Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer LC717A10AJ
Beschreibung Capacitance-Digital-Converter LSI
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 11 Seiten
LC717A10AJ Datasheet, Funktion
Ordering number : ENA2162
LC717A10AJ
CMOS LSI
Capacitance-Digital-Converter LSI
for Electrostatic Capacitive Touch
Sensors
http://onsemi.com
Overview
The LC717A10AJ is a high-performance and low-cost capacitance-digital-converter LSI for electrostatic capacitive
touch sensor, especially focused on usability.
It has 16 channels capacitance-sensor input. This makes it ideal for use in the products that need many switches.
Since the calibration function and the judgment of ON/OFF are automatically performed in LSI internal, it can make
development time more short. A detection result (ON/OFF) for each input can be read out by the serial interface (I2C
compatible bus or SPI).
Also, measurement value of each input can be read out as 8-bit digital data. Moreover, gain and other parameters can
be adjusted using serial interface.
Features
Detection system: Differential capacitance detection (Mutual capacitance type)
Input capacitance resolution: Can detect capacitance changes in the femto Farad order
Measurement interval (16 differential inputs): 30ms (Typ) (at initial configuration),
6ms (Typ) (at minimum interval configuration)
External components for measurement: Not required
Interface: I2C * compatible bus or SPI selectable.
Current consumption: 570μA (Typ) (VDD = 2.8V), 1.3mA (Typ) (VDD = 5.5V)
Supply voltage: 2.6V to 5.5V
Detection operations: Switch
Packages: SSOP30
* I2C Bus is a trademark of Philips Corporation.
Semiconductor Components Industries, LLC, 2013
August, 2013
Ver1.0.1
D1912HKPC 20121204-S00003 No.A2162-1/11






LC717A10AJ Datasheet, Funktion
LC717A10AJ
I2C Compatible Bus Slave Address
Selection of two kinds of addresses is possible through the SA0 and SA1 terminals.
SA1 input
SA0 input
7bit slave address
Binary notation
Low Low
0x16
00101100b (Write)
00101101b (Read)
Low High
0x17
00101110b (Write)
00101111b (Read)
High
Low
0x18
00110000b (Write)
00110001b (Read)
High
High
0x19
00110010b (Write)
00110011b (Read)
8bit slave address
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
SPI Data Timing (SPI Mode 0 / Mode 3)
nCS
tSU;SCK tSU;NCS tHIGH tLOW
tCPH
tr tf tHD;NCS tHD;SCK
SCK
tSU;SI tHD;SI
SI
SO
Hi-Z
VALID
tCLZ
tV
fig.5
tHD;SO
VALID
tCHZ
SPI Communication Formats (Example of Mode 0)
Write format (data can be written into sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
SO
Write=L
765432107654321076543210
Register Address(N)
Hi-Z
Data written to Register Address(N) Data written to Register Address(N+1)
fig.6
Read format (data can be read from sequentially incremented addresses with preserving nCS = L)
nCS
SCK
SI
SO
Read=H
76543210
Register Address(N)
Hi-Z
76543210765432107
Data read from Register Address(N) Data read from Register Address(N+1)
fig.7
No.A2162-6/11

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