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M93C56 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer M93C56
Beschreibung MICROWIRE Serial Access EEPROM
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
M93C56 Datasheet, Funktion
M93C86, M93C76, M93C66
M93C56, M93C46
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)
MICROWIRE® Serial Access EEPROM
FEATURES SUMMARY
Industry Standard MICROWIRE Bus
Single Supply Voltage:
– 4.5 to 5.5V for M93Cx6
– 2.5 to 5.5V for M93Cx6-W
– 1.8 to 5.5V for M93Cx6-R
Dual Organization: by Word (x16) or Byte (x8)
Programming Instructions that work on: Byte,
Word or Entire Memory
Self-timed Programming Cycle with Auto-
Erase: 5ms
Ready/Busy Signal During Programming
2MHz Clock Rate
Sequential Read Operation
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
Packages
– ECOPACK® (RoHS compliant)
Table 1. Product List
Reference
Part
Number
M93C86
M93C86 M93C86-W
M93C86-R
M93C76
M93C76 M93C76-W
M93C76-R
M93C66
M93C66 M93C66-W
M93C66-R
Reference
Part
Number
M93C56
M93C56 M93C56-W
M93C56-R
M93C46
M93C46 M93C46-W
M93C46-R
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
October 2005
1/31






M93C56 Datasheet, Funktion
M93C86, M93C76, M93C66, M93C56, M93C46
MEMORY ORGANIZATION
The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to VCC)
the x16 organization is selected; when Organiza-
tion Select (ORG) is connected to Ground (VSS)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to VSS or VCC for minimum
power consumption. Any voltage between VSS
and VCC applied to Organization Select (ORG)
may increase the stand-by current.
INTERNAL DEVICE RESET
In order to prevent inadvertent Write operations
during Power-up, a Power On Reset (POR) circuit
is included.
At Power-up and Power-down, the device must
not be selected (that is, the Chip Select Input (S)
must be driven Low) until the supply voltage
reaches the operating voltage VCC (as defined in
Tables 9, 10 and 11).
During Power-up (phase during which VCC is low-
er than VCCmin but increases continuously), the
device will not respond to any instruction until VCC
has reached the Power On Reset threshold volt-
age (this threshold is lower than the minimum VCC
operating voltage defined in DC AND AC PARAM-
ETERS). Once VCC has passed the POR thresh-
old, the device is reset.
Prior to selecting the memory and issuing instruc-
tions to it, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the instruction
and, for a Write instruction, until the completion of
the internal write cycle (tW).
During Power-down (phase during which VCC de-
creases continuously), as soon as VCC drops from
the normal operating voltage below the Power On
Reset threshold voltage, the device stops re-
sponding to any instruction sent to it.
ACTIVE POWER AND STANDBY POWER MODES
When Chip Select (S) is High, the device is select-
ed and in the Active Power mode. It consumes
ICC, as specified in Tables 15, 16, 17, 18 and 19.
When Chip Select (S) is Low, the device is dese-
lected.
If no Erase/Write cycle is in progress when Chip
Select goes Low, the device enters the Standby
Power mode, and the power consumption drops to
ICC1.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6-
W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
6/31

6 Page









M93C56 pdf, datenblatt
M93C86, M93C76, M93C66, M93C56, M93C46
READY/BUSY STATUS
While the Write or Erase cycle is underway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Se-
lect Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
When the Write cycle is completed, and Chip Se-
lect Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to re-
ceive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is
brought Low or until a new start bit is decoded.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (each byte contains FFh).
COMMON I/O OPERATION
Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
CLOCK PULSE COUNTER
In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the master (the microcontrol-
ler). This can lead to a misalignment of the instruc-
tion of one or more bits (as shown in Figure 7.) and
may lead to the writing of erroneous data at an er-
roneous address.
To combat this problem, the M93Cx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Cx6
family, are summarized in Table 5. to Table 7.. For
example, a Write Data to Memory (WRITE) in-
struction on the M93C56 (or M93C66) expects 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
Figure 7. Write Sequence with One Clock Glitch
S
C
D
START
"0"
"1"
WRITE
An
An-1
An-2
Glitch
D0
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT
AI01395
12/31

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