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S25FL129P Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer S25FL129P
Beschreibung 128-Mbit 3.0 V Flash Memory
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 



Gesamt 30 Seiten
		
S25FL129P Datasheet, Funktion
S25FL129P
128-Mbit 3.0 V Flash Memory
This product is not recommended for new and current designs. For new and current designs, S25FL128S supersedes S25FL129P.
This is the factory-recommended migration path. Please refer to the S25FL128S data sheet for specifications and ordering
information.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
Memory architecture
– Uniform 64 KB sectors
– Top or bottom parameter block (Two 64-KB sectors broken down
into sixteen 4-KB sub-sectors each)
– Uniform 256 KB sectors (no 4-KB sub-sectors)
– 256-byte page size
– Backward compatible with the S25FL128P (uniform 256 KB
sector) device
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Program operations are on a page by page basis
– Accelerated programming mode via 9V W#/ACC pin
– Quad Page Programming
Erase
– Bulk erase function
– Sector erase (SE) command (D8h) for 64 KB and 256 KB sectors
– Sub-sector erase (P4E) command (20h) for 4 KB sectors
(for uniform 64-KB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 KB sectors
(for uniform 64-KB sector device only)
Cycling endurance
– 100,000 cycles per sector typical
Data retention
– 20 years typical
Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
One time programmable (OTP) area for permanent, secure
identification; can be programmed and locked at the factory or by the
customer
CFI (Common Flash Interface) compliant: allows host system to
identify and accommodate multiple flash devices
Process technology
– Manufactured on 0.09 µm MirrorBit® process technology
Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-contact WSON package (6 x 8 mm)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
– 24-ball BGA (6 x 8 mm) package, 6 x 4 pin configuration
Performance Characteristics
Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
Power saving standby mode
– Standby Mode 80 µA (typical)
– Deep Power-Down Mode 3 µA (typical)
Memory Protection Features
Memory protection
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00648 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 24, 2015






S25FL129P Datasheet, Funktion
S25FL129P
3. Input/Output Descriptions
Signal
SO/IO1
SI/IO0
SCK
CS#
HOLD#/IO3
W#/ACC/IO2
VCC
GND
I/O
I/O
I/O
Input
Input
I/O
I/O
Input
Input
Description
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes.
Serial Data Input: Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual
and Quad I/O mode.
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI
on rising edge of SCK. Triggers output on SO after the falling edge of SCK.
Chip Select: Places device in active power mode when driven low. Deselects device and
places SO at high impedance when high. After power-up, device requires a falling edge on CS#
before any command is written. Device is in standby mode when a program, erase, or Write
Status Register operation is not in progress.
Hold: Pauses any serial communication with the device without deselecting it. When driven
low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS# also
be driven low. Functions as an I/O pin in Quad I/O mode.
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When
driven low, prevents any program or erase command from altering the data in the protected
memory area. Functions as an I/O pin in Quad I/O mode.
Supply Voltage
Ground
4. Logic Symbol
VCC
SI/IO0
SCK
CS#
W#/ACC/IO2
HOLD#/IO3
SO/IO1
GND
Document Number: 002-00648 Rev. *I
Page 7 of 66

6 Page







S25FL129P pdf, datenblatt
S25FL129P
7.9 Data Protection Modes
Cypress SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command
sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the
following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Register (WRR)
– Parameter 4 KB Sector Erase (P4E)
– Parameter 8 KB Sector Erase (P8E)
– Quad Page Programming (QPP)
– OTP Byte Programming (OTPP)
Software Protected Mode (SPM): The Block Protect BP2, BP1, BP0 bits define the section of the memory array that can
be read but not programmed or erased. Table 7.3 and Table 7.4 shows the sizes and address ranges of protected areas
that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write Disable (SRWD) bit
together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of a clock pulse
count that is a multiple of eight before executing them.
Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array)
Status Register Block
BP2 BP1 BP0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Protected
Address Range
None
FC0000h - FFFFFFh
F80000h - FFFFFFh
F00000h - FFFFFFh
E00000h - FFFFFFh
C00000h - FFFFFFh
800000h - FFFFFFh
000000h - FFFFFFh
Memory Array
Protected Sectors
Uniform
64 KB
Uniform
256 KB
Unprotected
Address Range
0 0 000000h - FFFFFFh
(4) SA255:SA252
(1) SA63 000000h - FBFFFFh
(8) SA255:SA248 (2)SA63:SA62 000000h - F7FFFFh
(16) SA255:SA240 (4)SA63:SA60 000000h - EFFFFFh
(32) SA255:SA224 (8)SA63:SA56 000000h - DFFFFFh
(64)SA255:SA192 (16)SA63:SA48 000000h - BFFFFFh
(128)SA255:SA128 (32)SA63:SA32 000000h - 7FFFFFh
(256)SA255:SA0 (64)SA63:SA0
None
Unprotected
Sectors
Uniform
64 KB
Uniform
256 KB
SA255:SA0 SA63:SA0
SA251:SA0 SA62:SA0
SA247:SA0 SA61:SA0
SA239:SA0 SA59:SA0
SA223:SA0 SA55:SA0
SA191:SA0 SA47:SA0
SA127:SA0 SA31:SA0
None
None
Protected Portion of
Total Memory Area
0
1/64
1/32
1/16
1/8
1/4
1/2
All
Table 7.4 TBPROT = 1 (Starts Protection from BOTTOM of Array)
Status Register Block
BP2
0
0
0
0
1
BP1
0
0
1
1
0
Protected
BP0 Address Range
0 None
1 000000h - 03FFFFh
0 000000h - 07FFFFh
1 000000h - 0FFFFFh
0 000000h - 1FFFFFh
Memory Array
Protected Sectors
Unprotected
Sectors
Uniform
64 KB
Uniform
256 KB
Unprotected
Address Range
Uniform
64 KB
Uniform
256 KB
0 0 000000h - FFFFFFh SA0:SA255 SA0:SA63
(4) SA0:SA3
(1) SA0 040000h - FFFFFFh SA4:SA255 SA1:SA63
(8) SA0:SA7
(2)SA0:SA1 080000h - FFFFFFh SA8:SA255 SA2:SA63
(16)SA0:SA15 (4)SA0:SA3 100000h - FFFFFFh SA16:SA255 SA4:SA63
(32)SA0:SA31 (8)SA0:SA7 200000h - FFFFFFh SA32:SA255 SA8:SA63
Protected Portion of
Total Memory Area
0
1/64
1/32
1/16
1/8
Document Number: 002-00648 Rev. *I
Page 13 of 66

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