PDF AX2061 Data sheet ( Hoja de datos )

Número de pieza	AX2061
Descripción	LCD Driver
Fabricantes	ON Semiconductor
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No Preview Available ! AX2061 LCD Driver for Low Multiplex Rates OVERVIEW The AX2061 is an LCD driver for low multiplex rates. Figure 1 shows the block diagram of the AX2061. The chip is controlled by a microcontroller using the SPI interface. The microcontroller writes pixel (segment) data into the pixel data memory. Display updates may be delayed using the pixel data latches. The pixel data latches drive the segment drivers, while the row counter drives the row drivers. Features • Single−chip LCD Controller/Driver 5 Row, 76 Segment Outputs • Wide Power Supply Range: from 2.2 V to 3.6 V • 4−bit Contrast Register • Selectable Row Drive Configuration: Static or 2/3/4/5 Row Multiplexing • Internal Generation of LCD Bias Voltages with Charge Pump from a Single 2.2 to 3.6 V Power Supply • 76 × 5−bit RAM for Display Data Storage • Auto−incremented Display Data Loading • Low Power Consumption • Internal 32 kHz Oscillator • SPI−Bus Interface BLOCK DIAGRAM www.onsemi.com ORDERING INFORMATION Device Package Shipping AX2061−1−WD1 Wafer/Die Contact Sales See additional information on page 16 of this data sheet. VDD ICLK RREF SYSCLK (32kHz) optional LATCH VSS SEL CLK MOSI MISO optional CAP Voltage Regulator / Pump Oscillator 32 kHz Frequency Divider Pixel Address Counter SPI Row Drivers Frame Counter ROW# ROW# SEG# Segment Drivers Pixel Latches Pixel Data Registers Figure 1. Functional Block Diagram of the AX2061 © Semiconductor Components Industries, LLC, 2016 March, 2016 − Rev. 3 1 Publication Order Number: AX2061/D 1 page AX2061 Table 5. LOGIC Symbol Description Digital Inputs VT+ Schmitt trigger low to high threshold point VT− Schmitt trigger high to low threshold point VIL Input voltage, low VIH Input voltage, high IL Input leakage current Digital Outputs IOH Output Current, high IOL Output Current, low Condition Min Typ Max Units 1.9 1.2 0.8 2.0 −1 1 V V V V mA VDD = 3 V, VOH = 2.4 V VDD = 3 V, VOL = 0.4 V 4 4 mA mA AC Characteristics Table 6. OSCILLATOR Symbol Description Condition fosc Internal oscillator frequency FREQ_OSC[3:0]=0101 FREQ_OSC[3:0]=1111 fext External clock input Input at pin SYSCLK (Note 1) Ndiv Clock frequency divider ratio Programmable via register DIVIDER REXT External resistor Between pin RREF and VSS (Note 2) 1. The usable frequency range will depend on the characteristics of the display used. 2. AX2061 will work with less accurate resistors, but the spread of fosc will be larger. Min Typ Max Units 25 32 39 kHz 20 0.02 32 80 kHz 1 222 0.99 1 1.01 MW www.onsemi.com 5 5 Page AX2061 SPI Timing SEL MOSI MISO T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 Tssd Ts Th Tcl Tch Tck Tst Figure 3. Serial Interface Timing Tx Rx Tssz CIRCUIT DESCRIPTION This section describes the bits of the register bank in detail. No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB. NOTE: Whole registers or register bits marked as reserved should be kept at their default values. NOTE: All addresses not documented here must not be accessed, neither in reading nor in writing. SPI Frame Formats SPI transactions start with a falling edge on SEL. The first four bits indicate the command, the following bits are interpreted according to the command bits. SPI transaction can be of variable length. The first 4 bits of each SPI transaction code the command to be executed by the AX2061. The first command bit, T0, distinguishes Write (0) from Read(1) accesses. The following three command bits (T1:T3) specify the register to access. Even though many registers can be read as well as written, reading a register is never required for the functionality of the AX2061. Register 000 (Pixel Data) has variable length, i.e. as many consecutive data elements as required can be read or written in a single SPI transaction. All other registers are twelve bits long. Table 13. REGISTER OVERVIEW Cmd Name Reset T1 :T2 :T3 11 10 9 8 000 PIXELDA −−−−− PIXELDATA… TA 010 CONFIG 0000 RST − CP DIV 0001 ENA CLK 0000 SRC 011 DIVIDER 0000 PRESCALER[3:0] 0000 0000 100 CONTRA 0000 REVISION[7:0] ST 0010 0111 101 PINCFG 0111 LAT LATCHDRV[2:0] 0111 CHR 0111 110 INT 0101 0000 0001 reserved CONTRAST_O FF[1 :0] 111 OSCILLA 0000 reserved TOR 0010 0011 Bit 7 6 5 4 3 210 FRM CLK SRC FRM SYNC DIVIDER[7:0] LATCH[1:0] MODE[3:0] CONTRAST[3:0] SYS CLKR SYSCLKDRV[2:0] reserved ICLKR ICLKDRV[2:0] BUF_CUR[3:0] CONF EN_OSC_ FREQ_OSC[3:0] PROG reserved Description Pixel Data Configuration Divider Contrast Pin Configuration Internal Configuration Oscillator frequency programming Pixel Data Register The first command bit, T0, distinguishes Write (0) from Read(1) accesses. The command code (T1:T2:T3 = 000) is followed by a 10 bit Pixel Address (PA), and two dummy bits. After that, Pixel Data (PD) can be read or written, one pixel at a time. The Pixel Address auto increments. An arbitrary number of consecutive pixels may be read or written in a single transaction. www.onsemi.com 11 11 Page

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