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AP0101CS Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer AP0101CS
Beschreibung High-Dynamic Range (HDR) Image Signal Processor
Hersteller ON Semiconductor
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Gesamt 30 Seiten
AP0101CS Datasheet, Funktion
AP0101CS HDR: Image Signal Processor (ISP)
Features
AP0101CS High-Dynamic Range (HDR)
Image Signal Processor (ISP)
AP0101CS Datasheet, Rev. 7
For the latest product datasheet, please visit www.onsemi.com
Features
• Supports ON Semiconductor sensors with up to
1.2 Mp (1280x960)
• 45 fps at 1.2 Mp, 60 fps at 720p
• Optimized for operation with HDR sensors
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz flicker
avoidance
• Adaptive Local Tone Mapping (ALTM)
• Test Pattern Generator
• Two-wire serial programming interface
• Interface to low-cost Flash or EPROM through SPI
bus (to configure and load patches)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Dual Band IR filter support
Applications
• SMPTE296 HDCCTV cameras
• Surveillance network IP cameras
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interface
Parallel
Primary camera input
format
Output interface
RAW12 Linear/Companded Bayer
data
Up to 20-bit Parallel1
Output format
YUV422 8-bit,10-bit, and
SMPTE296M
10-, 12-bit tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
Input clock range2
6-30 MHz
Maximum frame rate3 45 fps at 1.2 Mp, 60 fps at 720p
Maximum output clock
frequency
Parallel clock up to 84 MHz
VDDIO_S 1.8 or 2.8 V nominal
Supply VDDIO_H
voltage VDD_REG
2.5 or 3.3 V nominal
1.8V nominal
VDDIO_OTPM 2.5 or 3.3 V nominal
Operating temperature
(ambient - TA)
–30°C to +70°C
Typical power
consumption4
130 mW
Notes: 1. 20-bit in one pixel clock format is only available in
SMPTE mode with the use of 4 GPIOs.
2. With input clock below 10 MHz, the two wire
serial interface is supported only up to 100 KHz
3. Maximum frame rate depends on output inter-
face and data format configuration used.
4. 720p HDR 60 fps 74.25 MHz YCbCr_422_16
AP0101CS/D Rev. 7, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,






AP0101CS Datasheet, Funktion
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
The following table summarizes the key signals when using the internal regulator. (The
internal regulator has to be used for AP0101AT.)
Table 3:
Key Signals When Using the Regulator
Signal Name
VDD_REG
FB_SENSE
LDO_OP
Internal Regulator
1.8V
1.2V (input)
1.2V (output)
AP0101CS/D Rev. 7, 1/16 EN
6 ©Semiconductor Components Industries, LLC,2016.

6 Page









AP0101CS pdf, datenblatt
AP0101CS HDR: Image Signal Processor (ISP)
System Interfaces
Hard Reset
The AP0101CS enters the reset state when the external RESET_BAR signal is asserted
LOW, as shown in Figure 5. All the output signals will be in High-Z state.
Figure 5: Hard Reset Operation
t1
t2 t3
t4
EXTCLK
RESET_BAR
SDATA
All Outputs Data Active
Mode
Reset
Internal Initialization Time
Data Active
Enter streaming mode
Note: This assumes auto-config.
Table 8:
Hard Reset
Symbol
Definition
Min Typ Max Unit
t1 RESET_BAR pulse width
t2 Active EXTCLK required after RESET_BAR asserted
t3 Active EXTCLK required before RESET_BAR de-
asserted
50
10
10
EXTCLK
cycles
t4 First two-wire serial interface communication after 100
RESET_BAR is HIGH
Soft Reset
A soft reset sequence to the AP0101CS can be activated by writing to a register through
the two-wire serial interface.
Hard Standby Mode
The AP0101CS can enter hard standby mode by using the external STANDBY signal, as
shown in Figure 6.
Entering Standby Mode
1. Assert STANDBY signal HIGH.
Exiting Standby Mode
1. De-assert STANDBY signal LOW.
AP0101CS/D Rev. 7, 1/16 EN
12
©Semiconductor Components Industries, LLC,2016.

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