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AP0100CS Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer AP0100CS
Beschreibung High-Dynamic Range (HDR) Image Signal Processor
Hersteller ON Semiconductor
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Gesamt 30 Seiten
AP0100CS Datasheet, Funktion
AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0100CS Datasheet, Rev. 6
For the latest product datasheet, please visit www.onsemi.com
Features
• Up to 1.2Mp (1280x960) ON Semiconductor sensor
support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Applications
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interfaces
Parallel and HiSPi
Primary camera input
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Output interface
Output format
Analog composite, up to 16-bit
parallel digital output
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
NTSC output
720H x 487V
PAL output
720H x 576V
Input clock range
Supply voltage
6-30 MHz
VDDIO_S
VDDIO_H
VDD_REG
VDD
VDD_PLL
VDD_DAC
VDDIO_OTPM
1.8 or 2.8 V nominal
2.5 or 3.3 V nominal
1.8 V nominal
1.2 V nominal
1.2 V nominal
1.2V nominal
2.5 or 3.3 V nominal
VDDA_DAC
3.3 V nominal
Operating temp.
Power consumption
VDD_PHY
2.8 V nominal
–30°C to +70°C
185 mW
Notes: 1.
AP0100CS/D Rev. 6, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,






AP0100CS Datasheet, Funktion
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Figure 3: Typical HiSPi Configuration
Sensor IO
power
1.8V
( R egulator
IP)
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
DAC HiSPi
analog voltage
power
OTPM
power
Host IO
power
Sensor IO
power
VDDIO _S
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
TRIGGER_OUT
CLK_N CLK_P
DATA0_N DATA0_P
DATA1_N DATA1_P
G ND_REG
GND
VDDIO _H
S CLK
S DATA
S ADDR
EXTCLK
XTAL
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRST_BAR5
VDDIO_S6 VDD_REG4 LDO_OP4
VDDIO_OTPM VDDIO_H
VDDIO_DAC
VDDIO_PHY
HiSPi and Parallel Connection
When using the HiSPi interface, the user should connect the parallel interface to
VDDIO_S.
When using the parallel interface, the HiSPi interface and power supply (VDD_PHY) can
be left floating.
AP0100CS/D Rev. 6, Pub. 1/16 EN
6 ©Semiconductor Components Industries, LLC,2016.

6 Page









AP0100CS pdf, datenblatt
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
Power-Up Sequence
Powering up the ISP requires voltages to be applied in a particular order, as seen in
Figure 6. The timing requirements are shown in Table 6. The ISP includes a power-on
reset feature that initiates a reset upon power up of the ISP.
Figure 6: Power-Up and Power-Down Sequence
dv/dt
VDDIO_H
VDDIO_S, VDDIO_OTPM, VDDA_DAC,
VDD_PHY (when using HiSPi)
VDD_REG
EXTCLK
SCLK
SDATA
dv/dt
t1
dv/dt
t2
t3
t4
t7
t6
t5
Table 6: Power-Up and Power-Down Signal Timing
Symbol Parameter
t1 Delay from VDDIO_H to VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY
(When using HiSPi)
t2 Delay from VDDIO_H to VDD_REG
t3 EXTCLK activation
t4 First serial command1
t5 EXTCLK cutoff
t6 Delay from VDD_REG to VDDIO_H
t7 Delay from VDDIO_S, VDDIO_OTPM, VDDA_DAC, VDD_PHY (When using
HiSPi) to VDDIO_H
dv/dt Power supply ramp time (slew rate)
Min Typ Max
0 – 50
Unit
ms
0
t2 + 1
100
t6
0
0
50 ms
– ms
– EXTCLK cycles
– ms
50 ms
50 ms
– – 0.1
V/s
Note: 1. When using XTAL the settling time should be taken into account.
Reset
The AP0100CS has three types of reset available:
• A hard reset is issued by toggling the RESET_BAR signal
• A soft reset is issued by writing commands through the two-wire serial interface
• An internal power-on reset
Table 7 on page 13 shows the output states when the part is in various states.
AP0100CS/D Rev. 6, Pub. 1/16 EN
12
©Semiconductor Components Industries, LLC,2016.

12 Page





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