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STA380BW Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer STA380BW
Beschreibung 2.1-channel high-efficiency digital audio system
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
STA380BW Datasheet, Funktion
STA380BW
Sound Terminal®
2.1-channel high-efficiency digital audio system
Datasheet - production data
VQFN48 (7 x 7 mm)
Features
Wide-range supply voltage
– 4.5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
I2C control with selectable device address
Embedded full IC protection
– Manufacturing short-circuit protection (out
vs. gnd, out vs. vcc, out vs. out)
– Thermal protection
– Overcurrent protection
– Undervoltage protection
I2S interface, sampling rate 32 kHz ~ 192 kHz,
with internal sampling frequency converter for
fixed processing frequency
Three output power stage configurations
– 2.0 mode, L/R full bridges
– 2.1 mode, L/R two half-bridges, subwoofer
full bridge
– 2.1 mode, L/R full bridges, PWM output for
external subwoofer amplifier
Driving load capabilities
– 2 x 20 W into 8 ternary modulation
– 2 x 9 W into 4 + 1 x 20 W into 8
FFXTM 100 dB dynamic range
Fixed output PWM frequency at any input
sampling frequency
Embedded RMS meter for measuring real-time
loudness
New fully programmable noise-gating function
Up to 12 user-programmable biquads with
noise-shaping technology
Direct access to coefficients through I2C
shadowing mechanism
Fixed (88.2 kHz / 96 kHz) internal processing
sampling rate
Two independent DRCs configurable as a
dual-band anticlipper or independent
limiters/compressors (B2DRC)
Digital gain/att +48 dB to -80 dB with
0.125 dB/step resolution
Independent (fade-in, fade-out) soft volume
update with programmable rate 48 ~ 1.5 dB/ms
Bass/treble tones control
Audio presets: 15 crossover filters,
5 anticlipping modes, nighttime listening mode
STSpeakerSafeTM protection circuitry
– Pre- and post-processing DC blocking
filters
– Checksum engine for filter coefficients
– PWM fault self-diagnosis
STCompressorTM dual-band DRC
Table 1. Device summary
Order code
Package
Packing
STA380BW
STA380BWTR
VQFN48
VQFN48
Tray
Tape and Reel
April 2013
This is information on a product in full production.
DocID024543 Rev 1
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STA380BW Datasheet, Funktion
Contents
STA380BW
6.27
6.28
6.29
6.30
6.31
6.32
6.33
6.34
Short-circuit protection mode registers SHOK (address 0x58) . . . . . . . . 88
Extended coefficient range up to -4...4 (address 0x5A) . . . . . . . . . . . . . . 89
Miscellaneous registers (address 0x5C, 0x5D) . . . . . . . . . . . . . . . . . . . . 90
6.29.1 Rate power-down enable (RPDNEN) bit . . . . . . . . . . . . . . . . . . . . . . . . 90
6.29.2 Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . 90
6.29.3 Channel PWM enable (CPWMEN) bit . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.29.4 External amplifier hardware pin enabler (LPDP, LPD LPDE) bits . . . . . 91
6.29.5 Power-down delay selector (PNDLSL[2:0]) bits . . . . . . . . . . . . . . . . . . . 91
6.29.6 Short-circuit check enable bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Bad PWM detection registers (address 0x5E, 0x5F, 0x60) . . . . . . . . . . . 92
Enhanced zero-detect mute and input level measurement
(address 0x61-0x65, 0x3F, 0x40, 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . 93
STCompressorTM configuration register (address 0x6B; 0x6C) . . . . . . . . 95
Coefficient RAM CRC protection (address 0x71-0x7D) . . . . . . . . . . . . . . 96
MISC4 (address 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7 Register description: Sound Terminal compatibility . . . . . . . . . . . . . 100
7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.1.3 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2.1 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2.2 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.1 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.4.1 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.4.2 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4.3 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4.4 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.4.5 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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STA380BW pdf, datenblatt
List of tables
STA380BW
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . 106
Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . 107
Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Zero-crossing enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Output configuration engine selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Binary output mode clock loss detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LRCK double trigger protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Mute configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Master volume offset as a function of MVOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Channel volume as a function of CxVOL[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Bass management crossover frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . 125
Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Limiter attack threshold as a function of LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . 129
Limiter release threshold as a function of LxRT bits (AC mode). . . . . . . . . . . . . . . . . . . . 129
Limiter attack threshold as a function of LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . 130
Limiter release threshold as a function of LxRT bits (DRC mode) . . . . . . . . . . . . . . . . . . 130
RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . 137
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Extended attack rate, limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Extended attack rate, limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Extended biquad selector, biquad 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Extended biquad selector, biquad 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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