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PDF CY14V101PS Data sheet ( Hoja de datos )
| Número de pieza | CY14V101PS | |
| Descripción | 1-Mbit (128K x 8) Quad SPI nvSRAM | |
| Fabricantes | Cypress | |
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CY14V101PS
1-Mbit (128K × 8) Quad SPI nvSRAM
with Real Time Clock
Features
■ Density
❐ 1 Mbit (128K × 8)
■ Bandwidth
❐ 108-MHz high-speed interface
❐ Read and write at 54 MBps
■ Serial Peripheral Interface
❐ Clock polarity and phase modes 0 and 3
❐ Multi I/O option – Single SPI (SPI), Dual SPI (DPI), and Quad
SPI (QPI)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ One million STORE cycles to nonvolatile elements (SONOS
FLASH Quantum trap)
❐ Data retention: 20 years at 85 °C
■ Read
❐ Commands: Standard, Fast, Dual I/O, and Quad I/O
❐ Modes: Burst Wrap, Continuous (XIP)
■ Write
❐ Commands: Standard, Fast, Dual I/O, and Quad I/O
❐ Modes: Burst Wrap
■ Data protection
❐ Hardware: Through Write Protect Pin (WP)
❐ Software: Through Write Disable instruction
❐ Block Protection: Status Register bits to control protection
■ Special instructions
❐ STORE/RECALL: Transfer data between SRAM and
Quantum Trap nvSRAM
❐ Serial Number: 8-byte customer selectable (OTP)
❐ Identification Number: 4-byte Manufacturer ID and Product
ID
■ Store from SRAM to nonvolatile SONOS FLASH Quantum Trap
❐ AutoStore: Initiated automatically at power-down with a small
capacitor (VCAP)
❐ Software: Using SPI instruction (STORE)
❐ Hardware: HSB pin
■ Recall from nonvolatile SONOS FLASH Quantum Trap to
SRAM
❐ Auto RECALL: Initiated automatically at power-up
❐ Software: Using SPI instruction (RECALL)
■ Low-power modes
❐ Sleep: Average current = 380 µA at 85 °C
❐ Hibernate: Average current = 8 µA at 85 °C
■ Operating supply voltages
❐ Core VCC: 2.7 V to 3.6 V
❐ I/O VCCQ: 1.71 V to 2.0 V
■ Temperature range
❐ Industrial: –40 °C to 85 °C
■ Packages
❐ 16-pin SOIC
Functional Overview
The Cypress CY14V101PS combines a 1-Mbit nvSRAM with a
QPI interface. The QPI allows writing and reading the memory in
either a single (one I/O channel for one bit per clock cycle), dual
(two I/O channels for two bits per clock cycle), or quad (four I/O
channels for four bits per clock cycle) through the use of selected
opcodes.
The memory is organized as 128 Kbytes each consisting of
SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The
SRAM provides infinite read and write cycles, while the
nonvolatile cells provide highly reliable storage of data. Data
transfers from SRAM to the nonvolatile cells (STORE operation)
take place automatically at power-down. On power-up, data is
restored to the SRAM from the nonvolatile cells (RECALL
operation). The user can initiate the STORE and RECALL
operations through SPI instructions.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-94176 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2016
1 page  
Pin Definitions (continued)
Pin Name
I/O Type
INT/SQW
SI (I/O0)
SCK
NC
RFU
Output
Input
Input/Output
Input
–
–
CY14V101PS
Description
Interrupt output/calibration/square wave. Programmable to respond to the
clock alarm, the watchdog timer, and the power monitor. Also programmable
to either active HIGH (push or pull) or LOW (open drain). In calibration mode,
a 512-Hz square wave is driven out. In the square wave mode, you may
select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as
a continuous output.
Left unconnected if RTC feature is not used.
Serial Input. Pin for input of all SPI instructions and data.
I/O0: When the part is in dual or quad mode, the SI (I/O0) pin becomes I/O0
pin and acts as input/output.
Serial Clock. Runs at speeds up to a maximum of fSCK. Serial input is latched
at the rising edge of this clock. Serial output is driven at the falling edge of
the clock.
Not connected.
Reserved for future use.
Document Number: 001-94176 Rev. *I
Page 5 of 67
5 Page 
CY14V101PS
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and VCC crosses VSWITCH voltage.
As described earlier, at power-up nvSRAM performs a Power-Up
RECALL operation for tFA duration during which all memory
accesses are disabled. The HSB pin can be probed to check the
Ready/Busy status of nvSRAM after power-up.
The following is the device status after power-up:
■ SPI I/O Mode
■ Pull-ups activated for HSB
■ SO is tristated
■ Standby power mode if CS pin is high. Active power mode if
CS pin is LOW.
■ Status Register state:
❐ Write Enable bit is reset to ‘0’
❐ SRWD not changed from previous STORE operation
❐ SNL not changed from previous STORE operation
❐ Block Protection bits are not changed from previous STORE
operation
■ WP and NC (I/O3) functionality as defined by Quad Data Width
(QUAD) CR[1]. Pull-ups activated on WP and NC (I/O3) if Quad
Data width CR[1] is logic ‘0’.
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a AutoStore operation is performed (AutoStore is not
performed, if no write operations have been executed since the
last RECALL cycle). This feature prevents inadvertent writes to
nvSRAM from happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby state, and the CS follows the voltage applied on VCC.
Active Power Mode and Standby State
When CS is LOW, the device is selected and is in the active
power mode. The device consumes ICC (ICC1 + ICCQ1) current,
as specified in on page 55. When CS is HIGH, the device is
deselected and the device goes into the standby state time, if a
STORE or RECALL cycle is not in progress. If a
STORE/RECALL cycle is in progress, the device goes into the
standby state after the STORE or RECALL cycle is completed.
Document Number: 001-94176 Rev. *I
Page 11 of 67
11 Page | ||
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| PDF Descargar | [ Datasheet CY14V101PS.PDF ] | |
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