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CG7501AA Schematic ( PDF Datasheet ) - Cypress

Teilenummer CG7501AA
Beschreibung 4-Mbit (512 K x 8) nvSRAM
Hersteller Cypress
Logo Cypress Logo 




Gesamt 20 Seiten
CG7501AA Datasheet, Funktion
CG7501AA
4-Mbit (512 K × 8) nvSRAM
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
45 ns access time
Internally organized as 512 K × 8
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and recall cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20, –10operation
Industrial temperature
Package
48-ball fine-pitch ball grid array (FBGA)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CG7501AA is a fast static RAM (SRAM), with a
non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each. The embedded
non-volatile elements incorporate QuantumTrap technology,
producing the world’s most reliable non-volatile memory. The
SRAM provides infinite read and write cycles, while independent
non-volatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the non-volatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the non-volatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A 17
A 18
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
2048 X 2048
STORE
STATIC RAM
ARRAY
2048 X 2048
RECALL
COLUMN I/O
COLUMN DEC
A9 A10 A11A12 A13A14A15 A16
VCC VCAP
POWER
CONTROL
STORE/RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A14 A2
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-82292 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 5, 2012






CG7501AA Datasheet, Funktion
CG7501AA
only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by a software address sequence. The CG7501AA software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
Table 1. Mode Selection
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
CE WE OE A15–A0[3] Mode I/O Power
HXX
X
Not selected
Output high Z
Standby
LHL
X
Read SRAM
Output data
Active
LLX
X
Write SRAM
Input data
Active
L
H
L
0x4E38
Read SRAM
Output data
Active[4]
0xB1C7
Read SRAM
Output data
0x83E0
Read SRAM
Output data
0x7C1F
Read SRAM
Output data
0x703F
Read SRAM
Output data
0x8B45
AutoStore Disable Output data
Notes
3. While there are 19 address lines on the CG7501AA, only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care.
4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document Number: 001-82292 Rev. **
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CG7501AA pdf, datenblatt
Switching Waveforms (continued)
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [18, 19]
Address
CE
OE
Data Output
ICC
Address
CE
WE
Data Input
Data Output
Address Valid
tACE
tRC
tHZCE
tAA
tLZCE
tDOE
tHZOE
High Impedance
Standby
tLZOE
tPU
Active
Output Data Valid
tPD
Figure 6. SRAM Write Cycle #1 (WE Controlled) [19, 20, 21]
tWC
Address Valid
tSCE
tHA
tAW
tPWE
tSA
tSD tHD
Previous Data
tHZWE
Input Data Valid
tLZWE
High Impedance
Figure 7. SRAM Write Cycle #2 (CE Controlled) [ 19, 20, 21]
tWC
Address
Address Valid
tSA tSCE
tHA
CE
tPWE
WE
tSD tHD
Data Input
Input Data Valid
Data Output
High Impedance
Notes
18. WE must be HIGH during SRAM read cycles.
19. HSB must remain HIGH during read and write cycles.
20. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
21. CE or WE must be >VIH during address transitions.
Document Number: 001-82292 Rev. **
CG7501AA
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