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GD25D05B Schematic ( Datenblatt PDF ) - ELM

Teilenummer GD25D05B
Beschreibung Uniform sector dual and quad serial flash
Hersteller ELM
Logo ELM Logo 



Gesamt 28 Seiten
		
GD25D05B Datasheet, Funktion
http://www.elm-tech.com
GD25D05B
DATASHEET






GD25D05B Datasheet, Funktion
GD25D05BxIGx Uniform sector dual and quad serial flash
3. MEMORY ORGANIZATION
http://www.elm-tech.com
Each device has
64K
256
16
1/2
Each block has
64/32K
256/128
16/8
-
Each sector has
4K
16
-
-
Each page has
256
-
-
-
bytes
pages
sectors
blocks
Uniform Block Sector Architecture
Block
0
Sector
15
-----
0
00F000H
-----
000000H
Address range
00FFFFH
-----
000FFFH
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25D05B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25D05B supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands.
These commands allow data to be transferred to or from the device at two times the rate of the standard SPI.
When using the Dual Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1.
5. DATA PROTECTION
The GD25D05B provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will reset to 0 in the following situations:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected
memory area which is read-only and unalterable.
Hardware Protection Mode: WP# going low to protected the BP0~BP2 bits and SRP bits.
28 - 6
Rev.1.0

6 Page







GD25D05B pdf, datenblatt
GD25D05BxIGx Uniform sector dual and quad serial flash
7.5. Read Data Bytes (READ) (03H)
http://www.elm-tech.com
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-
in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, on the falling edge of SCLK. The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes
(READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure 5. Read Data Bytes Sequence Diagram
7.6. Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in on the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, on the
falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out.
Figure 6. Read Data Bytes at Higher Speed Sequence Diagram
28 - 12
Rev.1.0

12 Page


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