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L5150CS Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer L5150CS
Beschreibung 5V low dropout voltage regulator
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
L5150CS Datasheet, Funktion
L5150CJ
L5150CS
5 V low dropout voltage regulator
Datasheet - production data
'!0'03
PowerSSO-12
'!0'03
SO-8
Features
Max DC supply voltage
Max output voltage tolerance
Max dropout voltage
Output current
Quiescent current
1. Typical value
VS 40 V
Vo ±2%
Vdp 500 mV
Io 150 mA
Iqn 55 μA(1)
Operating DC supply voltage range
5.6 V to 40 V
Low dropout voltage
Low quiescent current consumption
Precision output voltage 5 V ±2%
Reset circuit sensing the output voltage
Programmable reset pulse delay with external
capacitor
Adjustable reset threshold
Early warning
Very wide stability range with low value output
capacitor
Thermal shutdown and short-circuit protection
Wide temperature range (Tj = -40 °C to 150 °C)
Description
L5150CJ and L5150CS are low dropout linear
regulators with microprocessor control functions
such as power on reset, low voltage reset, early
warning.
Typical quiescent current is 55 μA at very low
output current.
On chip trimming results in high output voltage
accuracy (2%). Accuracy is kept over wide
temperature range, line and load variation. Early
warning circuit monitors the input voltage and
compares it with an internal voltage reference.
Output voltage reset threshold can be adjusted
down to 3.5 V by means of an external voltage
divider.
The maximum input voltage is 40 V. The max
output current is internally limited. Internal
temperature protection disables the voltage
regulator output. In addition, only low-value
ceramic capacitor on output is required for
stability.
Package
PowerSSO-12
SO-8
Table 1. Device summary
Order codes
Tube
L5150CJ
L5150CS
Tape & reel
L5150CJTR
L5150CSTR
June 2015
This is information on a product in full production.
DocID15542 Rev 16
1/34
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L5150CS Datasheet, Funktion
Block diagram and pins description
Pin name
PowerSSO-12
pin #
Res_Adj
1
Res 2
Vcr
GND
NC
Vo
VS
EWi
3
4
5, 11, 8, 9
6
7
10
EWo
12
TAB -
L5150CJ / L5150CS
Table 2. Pins description
SO-8
pin #
Function
Reset adjustable threshold. Connected to an
8
appropriate external voltage divider, it allows to
properly set the reset threshold down to 3.5 V.
Connect to GND if not needed.
Reset output. Internally connected to Vo through a
1 20 Kpull up resistor. This pin is pulled low when
Vo < Vo_th. Keep open if not needed.
Reset delay. Connect an external capacitor between
2 Vcr pin and ground to adjust the reset delay time.
Keep open if not needed.
3 Ground reference.
- Not connected.
4
5 V regulated output. Block to GND with a ceramic
capacitor (Co 220 nF for regulator stability).
5
Supply voltage, block directly to GND on the IC with a
capacitor.
Early warning input. This pin monitors the VS voltage
6 level through a resistor divider. Connect to VS if not
needed.
Early warning output. Internally connected to Vo
7
through 20 Kpull up resistor. This pin is pulled low
when EWi is below bandgap reference voltage. Keep
open if not needed.
TAB is connected to the substrate of the chip: connect
- toGND or leave open (see Figure 2 for PowerSSO-12
only).
6/34 DocID15542 Rev 16

6 Page









L5150CS pdf, datenblatt
Electrical specifications
L5150CJ / L5150CS
Figure 9. Current consumption vs. input voltage
(Io = 75 mA)
Figure 10. Current limitation vs. Tj
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Figure 11. Current limitation vs. input voltage
Figure 12. Short-circuit current vs. Tj
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Figure 13. Short-circuit current vs. input
voltage
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Figure 14. VRhth vs. Tj
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12/34
DocID15542 Rev 16

12 Page





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