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PDF MCP19116 Data sheet ( Hoja de datos )

Número de pieza MCP19116
Descripción Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller
Fabricantes Microchip 
Logotipo Microchip Logotipo



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No Preview Available ! MCP19116 Hoja de datos, Descripción, Manual

MCP19116/7
Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller
with Improved 8k Word Core
Features
• Input Voltage: +4.5V to +42V
• Can be configured with multiple topologies includ-
ing but not limited to:
- Flyback
- Ćuk
- Boost
- SEPIC (Single-Ended Primary-Inductor
Converter)
• Capable of Quasi-Resonant or Fixed-Frequency
Operation
• Low Quiescent Current: 5 mA Typical
• Low Sleep Current: 50 µA Typical
• Low-Side Gate Drivers:
- +5V gate drive with 0.5A sink/source current
- +10V gate drive with 1A sink/source current
• Peak Current Mode Control
• Differential Remote Output Sense
• Multiple Output Systems:
- Master or Slave
• AEC-Q100 Qualified
• Configurable Parameters:
- VREF, Precision IOUT/VOUT Set Point (DAC)
- ADC Reference Switch (VDD or AVDD)
- Input Undervoltage Lockout (UVLO)
- Input Overvoltage Lockout (OVLO)
- Detection and protection
- Primary current leading edge blanking (0 ns,
50 ns, 100 ns and 200 ns)
- Gate drive dead time (16 ns to 256 ns)
- Fixed switching frequency range:
31.25 kHz to 2.0 MHz
- Slope compensation
- Quasi-Resonant configuration with built-in
comparator and programmable offset voltage
adjustment
- Primary current offset adjustment
- GPIO pin options
• Integrated Low-Side Differential Current-Sense
Amplifier
• Better than 5% Current Regulation
• Thermal Shutdown
Microcontroller Features
• Precision 8 MHz Internal Oscillator Block:
- Factory-calibrated to ±1%, typical
• Interrupt-Capable:
- Firmware
- Interrupt-on-change pins
• Only 35 Instructions to Learn
• 8192 Words On-Chip Program Memory
• High-Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: > 40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Eight I/O Pins and One Input-Only Pin:
- Two open-drain pins
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Five external channels
• Timer0: 8-bit Timer/Counter with 8-bit Prescaler
• Enhanced Timer1:
- 16-bit timer with prescaler
- Two selectable clock sources
• Timer2: 8-Bit Timer with Prescaler:
- 8-bit period register
• I2C Communication:
- 7-bit address masking
- Two dedicated address registers
• Addressable Universal Synchronous Receiver
Transmitter (AUSART) Modes
- Asynchronous (Full Duplex)
- Synchronous - Master (Half Duplex)
- Synchronous - Slave (Half Duplex)
2015-2016 Microchip Technology Inc.
DS20005479B-page 1

1 page




MCP19116 pdf
TABLE 2: 28-PIN QFN (MCP19117) SUMMARY
MCP19116/7
Basic
Additional
GPA0
1 Y AN0
— IOC Y
Analog/Digital Debug Output (1)
GPA1
2 Y AN1
— IOC Y
Sync Signal In/Out (2)
GPA2 3 Y AN2 T0CKI — IOC Y
INT
——
GPA3
5 Y AN3
— IOC Y
——
GPA5
8N
IOC (3) Y (4)
MCLR Test Enable Input
GPA6
7N
— IOC Y
— Dual Capture / Single
Compare1 Input
GPA7
6N
— SCL IOC N
——
GPB0 10 N
— SDA IOC N
——
GPB1 26 Y AN4
— IOC Y
— VREF2 (5)
GPB4
4 Y AN5
— IOC Y ICSPDAT —
GPB5 27 Y AN6
— IOC Y ICSPCLK —
GPB6 28 Y AN7
— TX/CK IOC
Y
——
GPB7 9 Y
— RX/DT IOC
Y
— Single Compare2 Input
DESATP/ 12 N
ISOUT
— DESATP Input or ISOUT
Output (6)
DESATN 11 N
ISP
13 N
Y
— DESAT Negative Input
— Current Sense Amplifier
Non-inverting Input
ISN 14 N — — — — —
— Current Sense Amplifier
Inverting Input
IP
15 N
AGND
16 N
PGND
17 N
SDRV 18 N
AGND
PGND
Primary Input Current Sense
Small Signal Ground
Large Signal Ground
Secondary LS Gate Drive
Output
PDRV 19 N
— Primary LS Gate Drive Output
VDR
VDD
VIN
VS
IFB
ICOMP
Note 1:
20 N
21 N
22 N
23 N
VDR Gate Drive Supply Voltage
VDD
VDD Output
VIN Input Supply Voltage
— Output Voltage Sense
24 N
— Error Amplifier Feedback input
25 N
— Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
3: The IOC is disabled when MCLR is enabled.
4: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
5: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
6: When RFB of MODECON<6> = 0, the internal feedback resistor is enabled allow with DESATP input.
When RFB = 1, ISOUT is enabled.
2015-2016 Microchip Technology Inc.
DS20005479B-page 5

5 Page





MCP19116 arduino
MCP19116/7
FIGURE 1-2:
MCP19116 ĆUK SYNCHRONOUS POSITIVE OUTPUT APPLICATION DIAGRAM
VIN
EN
DIMI
VDD
TEMP SNS 2
VDD
BIN 2
TC1240
VOLTAGE
DOUBLER
5V
10V
VIN
MCLR
VDR VDD
CCD
PDRV
MCP19116 IP
I/O DESATN
DESATP
SDRV
ISN
I/O ISP
IFB
I/O
AGND
ICOMP
PGND
VS
I/O
I/O
FIGURE 1-3:
MCP19116 BOOST QUASI-RESONANT APPLICATION DIAGRAM
VIN
DESATN DESATP
5V
EN
DIMI
VDD SW1
SW2
TEMP SNS
VIN
MCLR
VDR VDD
CCD
PDRV
IP
I/O DESATN
DESATP
I/O MCP19116 ISOUT
IFB
2
I/O
ICOMP
VDD
BIN 2 I/O
ISP
ISN
VS
SDRV
AGND
PGND
DESATN
DESATP
SW1
SW2
2015-2016 Microchip Technology Inc.
DS20005479B-page 11

11 Page







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