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EQCO31R20.3 Schematic ( PDF Datasheet ) - Microchip

Teilenummer EQCO31R20.3
Beschreibung 3.125 Gbps Asymmetric Coax Equalizer
Hersteller Microchip
Logo Microchip Logo 




Gesamt 30 Seiten
EQCO31R20.3 Datasheet, Funktion
EQCO62R20.3/EQCO31R20.3
EQCO62R20.3 6.25 Gbps Asymmetric Coax Equalizer/
EQCO31R20.3 3.125 Gbps Asymmetric Coax Equalizer
Features
• Complies with the CoaXPress v1.1 camera
standard (1)
• Supports up to 68 meters of cable at 6.25 Gbps
using high-quality coax
• Supports up to 212 meters of cable at 1.25 Gbps
using high-quality coax
• Single-chip solutions for both the camera side and
the frame grabber side, making a bidirectional
connection over a single 75coax cable
• Full-Duplex, bidirectional data channel
- Downlink speeds from 1.25 Gbps up to 6.25
Gbps; differential interfacing straightforward
with internal termination resistors
- Uplink supporting 21 Mbps, allowing
nanoseconds precise triggering events driven
by the frame grabber
• Supports power distribution over the coax up to
900 mA, powering the camera through the same
coax transporting data signals
• Low power consumption (<70 mW, 1.2V supply)
• 16-Pin, 0.65 mm pin pitch, 4 mm QFN package
• Small PCB footprint for EQCO62R20 and off-chip
components, with guaranteed RF-performance
• -40°C to +85°C industrial temperature range
• Pb-free and RoHS compliant
Applications
• High-definition/high-bandwidth links to cameras
• Machine vision for semiconductor chips and
display panel inspection systems
• Military, aerospace, medical applications
• Broadcast and surveillance camera systems
• Traffic license plate and monitoring systems
• High-Speed inspection systems for food Inspection,
bottling inspection, panel inspection, etc.
• Any application requiring a single coax cable
which carries power, video data and camera
control stream.
Introduction
The EQCO62T/R20(2) chipset is a driver/equalizer
chipset that forms a bidirectional, full-duplex
communication link over a single coax cable.
The EQCO62T/R20 chipset is designed to transport up
to 6.25 Gbps over the downlink channel and to trans-
port 21 Mbps over the uplink channel. The
EQCO62T20 is designed to transmit the downlink sig-
nal at up to 6.25 Gbps and receive the uplink signal.
The EQCO62R20 is designed to receive the downlink
signal at up to 6.25 Gbps and to transmit the uplink sig-
nal. Power can be transferred over the same cable via
external inductors.
The chipset is designed to work with several types of
75coaxial cables, including legacy cables as well as
thin, flexible lightweight cables.
Note 1: CoaXPress V1.1 standard. Free down-
load from the JIIA website:
http://jiia.org/en/standardization/list/
2: The EQCO31T20 and EQCO31R20 are
lower-speed versions of the EQCO62T20
and EQCO62R20, with a maximum bit
rate of 3.125 Gbps for the high-speed
downlink and the same uplink speed.
2012-2016 Microchip Technology Inc.
DS60001302B-page 1






EQCO31R20.3 Datasheet, Funktion
EQCO62R20.3/EQCO31R20.3
1.1.1 SDIp/SDIn
SDIp/SDIn together form a differential input pair. It is
the differential voltage between these pins that the
EQCO62R20 analyzes and adaptively equalizes for
signal level and frequency response. The equalizer
automatically detects and adapts to signals with
different edge rates, different attenuation levels and
different cable characteristics. Both SDIp and SDIn
inputs are terminated by 60to VCC on-chip. For each
input, an external 15resistor is required in series.
1.1.2 SDOp/SDOn
SDOp/SDOn together form a differential pair, outputting
the reconstructed far-end transmit signal. SDOp/SDOn
are terminated on-chip with 2x50resistors.
1.1.3 LFI
LFI is the uplink input signal that will be transmitted on
the SDIp/SDIn pair. LFI must be a 1.2V LVTTL signal.
For 2.5V and 3.3V input swing, an external resistor is
needed in series at the input of the chip.
1.1.4 AmpR
AmpR is a VCC resistor that sets the transmit
amplitude of the uplink output driver. The typical
value for CoaXPress is Ramp = 1.2 kfor 130 mV
transmit amplitude.
1.1.5 RISER
RiseR is a VCC resistor that selects the rise/fall time of
the uplink output driver. The typical value for
CoaXPress is Rrise = 10 kfor rise/fall time of 11 ns.
If no Ramp and Rrise are placed, the LF driver is disabled.
DS60001302B-page 6
2012-2016 Microchip Technology Inc.

6 Page









EQCO31R20.3 pdf, datenblatt
EQCO62R20.3/EQCO31R20.3
2.1.2
MULTILANE COAXPRESS 4+1
LAYOUT WITH DIN1.0/2.3
CONNECTORS
Figure 2-3 shows an example of a Multilane
CoaXPress 4+1 setup. The recommended Din1.0/2.3
connector is the NPF 4076 from Cambridge
Connectors. The cable example shows the pitches in
millimeters. Figure 2-4 shows the four layers of the
recommended footprints and off-chip components that
are critical for RF-performance of the cable drivers
CD_1 to CD_4 at the camera side, which have Power
over CoaXPress (PoCXP). Figure 2-5 shows the
variant without PoCXP used for CD_5 at the host side.
The exact dimensions in millimeters are given in
Section 4.1 “Package Marking Information”. It is
recommended to copy these dimensions, especially
the connection between the DIN1.0/2.3 connector and
the chip, as this is a complex entity with coupled
currents and compensated parasitic capacitances.
Despite the critical layout, this proposed layout is
designed to be largely independent of the used PCB-
layer stack, as the critical parts are mainly the top-layer
only. This will work as well for four, six or even higher
numbers of layers. Possible extra layers should have
cut-outs as large as the full proposed footprint.
In these layouts, the size of the PCB area needed for
the chip is minimized. This allows multiple lanes
close together.
Only two of four connector GND pins are connected to
the GND plane to reduce the capacitance.
The differential CD inputs must be a 100differential
transmission line. A cut-out of the ground and power
plane underneath the input pins is recommended to
minimize the parasitic capacitance. For best
performance, no vias should be used in this high-speed
signal path.
The Components Express 4+1 connector in Figure 2-3 is
only shown as an example. Other connector
configurations are available with DIN1.0/2.3 connectors
such as 6+1, 2+1, 1+1, dual- or single-lane configurations.
DS60001302B-page 12
2012-2016 Microchip Technology Inc.

12 Page





SeitenGesamt 30 Seiten
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